Am186™ES and Am188™ES
User’s Manual
© 1997 Advanced Micro Devices, Inc.
All rights reserved.
Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in
its products without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make
changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this
publication.
This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of
merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or
systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of
engineering samples) of AMD products except as provided in AMD’s Terms and Conditions of Sale for such products.
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386 and Am486 are registered trademarks, and Am186, Am188, E86, AMD Facts-On-Demand,
and K86 are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU.
Customer Service
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™
family hardware
and software development questions.
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Documentation and Literature
Free E86 family information such as data books, user’s manuals, data sheets, application
notes, the FusionE86
SM
Partner Solutions Catalog, and other literature is available with a
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TABLE OF CONTENTS
PREFACE
INTRODUCTION AND OVERVIEW
DESIGN PHILOSOPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PURPOSE OF THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTENDED AUDIENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USER’S MANUAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMD DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E86 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CHAPTER 1
FEATURES AND PERFORMANCE
1.1 KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 DISTINCTIVE CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 APPLICATION CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
PROGRAMMING
2.1 REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1 Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 MEMORY ORGANIZATION AND ADDRESS GENERATION . . . . . . . . . 2-3
2.3 I/O SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.5 SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.6 DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
SYSTEM OVERVIEW
3.1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Pins That Are Used by Emulators . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.2 BUS OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.3 BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.3.1 Nonmultiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.3.2 Static Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.3.3 Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.3.4 Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . . 3-24
3.4 CLOCK AND POWER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . 3-25
3.4.1 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.2 Crystal-Driven Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.3 External Source Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.4.4 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.4.5 Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
PERIPHERAL CONTROL BLOCK
4.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Peripheral Control Block Relocation Register
(RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.2 Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . . 4-4
4.1.3 Processor Release Level Register (PRL, Offset F4h) . . . . . . . . . . 4-5
4.1.4 Auxiliary Configuration Register (AUXCON, Offset F2h). . . . . . . . 4-6
4.1.5 System Configuration Register (SYSCON, Offset F0h) . . . . . . . . 4-7
CHAPTER 2
CHAPTER 3
CHAPTER 4
Table of Contents
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