BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
DESCRIPTION
BS616UV8021
• Ultra low operation voltage : 1.8 ~ 2.3V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=2.0V
-10 100ns (Max.) at Vcc=2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616UV8021 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616UV8021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8021 is available in DICE form and 48-pin BGA type.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616UV8021DC
BS616UV8021BC
BS616UV8021FC
BS616UV8021DI
BS616UV8021BI
BS616UV8021FI
OPERATING
TEMPERATURE
SPEED
(ns)
Vcc=2.0V
Vcc RANGE
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=2.0V
Vcc=2.0V
+0 C to +70 C
O
O
O
O
1.8V ~ 2.3V
70 / 100
15uA
20mA
-40 C to +85 C
1.8V ~ 2.3V
70 / 100
20uA
25mA
DICE
BGA-48-0810
BGA-48-0912
DICE
BGA-48-0810
BGA-48-0912
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
A18
2
OE
UB
D10
D11
D12
D13
CIO
.
A8
3
A0
A3
A5
A17
Vss
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
6
CE2
D0
D2
VCC
VSS
D6
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A17
A7
A6
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
4096
D0
16(8)
Data
Input
Buffer
16(8)
Column I/O
.
.
.
.
D15
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
.
.
.
.
Write Driver
16(8)
Sense Amp
256(512)
Column Decoder
16(8)
Data
Output
Buffer
16(18)
Control
Address Input Buffer
WE
A11
D7
SAE
.
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
48-Ball CSP top View
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
R0201-BS616UV8021
1
Revision 2.2
April 2001
BSI
PIN DESCRIPTIONS
Preliminary
BS616UV8021
Name
A0-A18 Address Input
SAE Address Input
CIO x8/x16 select input
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
This address input incorporate with the above 19 address inputs select one of the
1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
This input selects the organization of the SRAM. 524,288 x 16-bit words configuration
is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Gnd
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
R0201-BS616UV8021
2
Revision 2.2
April 2001
BSI
TRUTH TABLE
MODE
CE1
H
Fully Standby
X
Output Disable
L
L
H
H
H
X
CE2
X
X
X
X
X
X
L
L
H
L
H
H
H
L
L
L
( WORD mode )
H
X
L
H
H
L
Read from SRAM
L
( BYTE Mode )
Write to SRAM
L
( BYTE Mode )
H
X
L
L
X
X
A-1
H
L
H
L
X
X
X
H
L
L
H
L
L
X
A-1
X
X
X
OE
WE
CIO
LB
X
UB
X
X
SAE
BS616UV8021
D0~7
D8~15
VCC Current
High- Z
High- Z
I
CCSB
, I
CCSB1
High-Z
Dout
High-Z
Dout
Din
X
Din
Dout
High- Z
High- Z
Dout
Dout
X
Din
Din
High-Z
I
CC
Read from SRAM
( WORD mode )
I
CC
Write to SRAM
I
CC
I
CC
Din
X
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +125
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
1.8V ~ 2.3V
1.8V ~ 2.3V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not tested.
R0201-BS616UV8021
3
Revision 2.2
April 2001
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C)
PARAMETER
NAME
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
I
CC
I
CCSB
BS616UV8021
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
TEST CONDITIONS
Vcc=2.0V
Vcc=2.0V
MIN.
-0.5
1.4
--
--
Vcc=2.0V
TYP.
(1)
MAX.
--
--
--
--
--
--
--
--
0.6
Vcc+0.2
UNITS
V
V
uA
uA
V
V
mA
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1 = V
IH
, or CE2 = V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc= max, I
OL
= 1mA
Vcc= Min, I
OH
= -0.5mA
1
1
0.4
--
20
0.6
--
1.6
--
--
Vcc=2.0V
Operating Power Supply Vcc= max, CE1=V
IL
and CE2 = V
IH
,
Current
I
DQ
= 0mA, F =Fmax
(3)
Standby Current- TL
T
Vcc= max, CE1 = V
IH
or CE2 = V
IL
,
I
DQ
= 0mA
Vcc= max,CE1 Vcc-0.2V,
or CE2 0.2V;V
IN
Vcc - 0.2V or
V
IN
0.2V
Vcc=2.0V
Vcc=2.0V
I
CCSB1
Standby CurrentCMOS
-
Vcc=2.0V
--
0.6
15
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/ t
RC
.
R0201-BS616UV8021
4
Revision 2.2
April 2001
BSI
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to +70
o
C )
SYMBOL
V
DR
BS616UV8021
TEST CONDITIONS
CE1
V
IN
CE1
V
IN
Vcc - 0.2V or CE2
0.2V ;
Vcc - 0.2V or V
IN
0.2V
Vcc - 0.2V or CE2
0.2V
Vcc - 0.2V or V
IN
0.2V
PARAMETER
Vcc for Data Retention
MIN. TYP.
1.5
--
(1)
MAX.
--
UNITS
V
I
CCDR
Data Retention Current
Chip Deselect to Data
Retention Time
--
0.4
10
uA
t
CDR
t
R
0
See Retention Waveform
T
RC (2)
--
--
--
--
ns
ns
Operation Recovery Time
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
1.5V
Vcc
t
CDR
CE1
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
1.5V
Vcc
t
CDR
t
R
CE2
0.2V
CE2
V
IL
V
IL
R0201-BS616UV8021
5
Revision 2.2
April 2001
嵌入式系统
