CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Supply Voltage
(See Figure 1)
TEST CONDITIONS
TEMP. (
o
C)
25
MIN
8
TYP
-
MAX
9
UNITS
V
S
1
, S
5
, S
6
= 2; S
2
, S
3
, S
4
, S
7
, S
8
= 1
Measure Terminal 6 to GND
S
1
, S
5
, S
6
= 2; S
2
, S
3
, S
4
, S
7
, S
8
= 1
Counter to Terminal 1
S
2
, S
3
, S
6
, S
8
= 1; S
1
, S
4
, S
5
, S
7
= 2
Measure Terminal 1 to 25V
S
2
, S
3
, S
5
, S
6
, S
8
= 1; S
1
, S
4
, S
7
= 2
Measure Terminal 1 to GND
S
2
, S
5
, S
6
, S
8
= 1; S
1
, S
3
, S
4
, S
7
= 2
Measure Terminal 3 to GND
S
5
, S
8
= 1; S
1
, S
2
, S
3
, S
4
, S
6
, S
7
= 2
Measure Terminal 5 to +4V
S
1
, S
5
, S
8
= 1; S
2
, S
3
, S
4
, S
6
, S
7
= 2
Measure Terminal 5 to +4V
S
1
, S
5
, S
6
, S
8
= 1; S
2
, S
3
, S
4
, S
7
= 2
Measure Terminal 5 to +4V
Free Running
Frequency -1%
Output Leakage
25
14734
-
16734
Hz
25
-
10
-
mV
Output Saturation
25
-
60
-
mV
Phase Detector Bias
25
-
1.9
-
V
Phase Detector Leak
25
-2
-
2
mV
Phase Detector Low
25
-0.55
(Note 2)
+0.55
(Note 2)
-100
0.3
-
-
-
-
-
V
Phase Detector High
25
-
-
V
Phase Detector Balance V
DET2
+ V
DET3
Sync Diode
Static Phase Error
Oscillator Pull In Range
Oscillator Hold In Range
NOTE:
2. Polarity reversed in the CA1391.
S
1
, S
2
, S
3
, S
4
, S
6
, S
7
= 1; S
5
, S
8
= 2
See Figure 3
25
25
25
-
-
0.5
±300
±900
100
1.2
-
-
-
mV
V
µs
Hz
Hz
8-10
CA1391, CA1394
Test Circuit
+25V
620Ω
1W
1kΩ
1
14kΩ
S
3
430Ω
2
S
5
1.5kΩ
1
S
4
8
7
CA1391/CA1394
1
2
S
8
2.65kΩ
1
2
5.6kΩ
+6V
1
3
S
1
2
1
4
S
2
2
6
5
2 1
S
6
1
150kΩ
1µF
6800pF
1
2
S
7
150Ω
2
100Ω
1.65kΩ
2
150Ω
+6V
200Ω
FIGURE 1. DC TEST CIRCUIT
Schematic Diagram
PRE-
DRIVER
OSC.
TIMING
7
OSCILLATOR
R
8
3.9K
R
1
2.6K
Q
6
R
12
2.4K
R
16
1.1K
R
18
200
Q
15
Z
2
V+
6
REGULATOR
PHASE
DETECTOR
R
31
560
R
24
40K
Q
16
R
29
1.5K
R
30
1.5K
Q
20
Q
21
5
PHASE
DET. OUT
CA1394E
4
MARK-
SPACE
RATIO
8
Q
3
OUT
1
Q
1
Q
2
R
15
2.4K
Q
4
R
4
430
R
3
7.5K
Q
5
R
6
400
R
5
5.1K
R
2
6.8K
2 GND
R
7
1.8K
Q
9
R
10
470
Q
10
Q7 Q
8
R
9
1.3K
R
14
6.8K
Q
11
R
13
1.5K
Z
1
R
1
3K
Q
19
Q
14
Q
12
Q
13
R
17
6.2K
R
22
3.3K
R
20
820
R
23
6.8K
R
25
7.5K
R
26
Q
22
Q
23
HORIZ
INPUT
4
CA1391E
7.5K
Q
18
Q
17
R
27
510
D
1
R
11
3.6K
R
19
240
D
2
R
28
910
3 SYNC INPUT
NOTE: All resistances are in ohms.
8-11
CA1391, CA1394
Application Information
Circuit Operation
(See Schematic Diagram)
The CA1391 and CA1394 contain the oscillator, phase
detector, and predriver sections necessary for the television
horizontal oscillator and AFC loop.
The oscillator is an RC type with Terminal 7 used to control the
timing. If it is assumed that Q
7
is initially off, then an external
capacitor connected from Terminal 7 to ground charges through
an external resistance connected between Terminals 6 and 7. As
soon as the voltage at Terminal 7 exceeds the potential set at the
base of Q
8
by resistors R
11
and R
12
, Q
7
turns on, and Q
6
sup-
plies base current to Q
5
and Q
10
. Transistor Q
5
discharges the
capacitor through R
4
until the base bias of Q
7
falls below that of
Q
8
at which time, Q
7
turns off, and the cycle repeats.
The sawtooth generated at the base of Q
4
appears across R
3
and turns off Q
3
whenever the sawtooth voltage rises to a value
that exceeds the bias set at Terminal 8. By adjusting the poten-
tial at Terminal 8, the duty cycle at the pre-drive output (Termi-
nal 1) may be changed. The phase detector is isolated from the
remainder of the circuit by R
31
, Z
2
, Q
15
and Q
16
. The phase
detector consists of the comparator Q
22
and Q
23
, and the
gated current source Q
18
. Negative going sync pulses at Ter-
minal 3 turn off Q
17
, and the current division between Q
22
and
Q
23
is then determined by the phase relationship of the sync
and the sawtooth waveform at Terminal 4, which is derived from
the horizontal flyback pulse. If there is no phase difference
between the sync and sawtooth, equal currents flow in the col-
lectors of Q
22
and Q
23
during each half of the sync pulse
period. The current in Q
22
is turned around by current mirror
Q
20
and Q
21
so that there is no net output current at Terminal 5
for balanced conditions. When a phase offset occurs, current
flows either in or out of Terminal 5. In circuit applications, this
terminal is connected to Terminal 7 through an external low
pass filter, thereby controlling the oscillator.
Shunt regulation for the circuit is obtained by using a V
BE
and zener multiplier. Resistors R
13
and R
14
multiply the V
BE
of Q
11
, and the ratio of R
15
and R
16
multiplies the voltage of
the zener diode Z
1
.
T
A
= 25
o
C
FREE RUNNING FREQUENCY = 15734Hz
VOLTAGE AT TERM. 8 (THROUGH 1kΩ)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0
10
20
30
40
50
60
70
POSITIVE PULSE WIDTH AT TERMINAL 1 (µs)
FIGURE 2. DUTY CYCLE AT THE PRE-DRIVE OUTPUT (TERMINAL
