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CAT5411B-25-TE13

Digital Potentiometer, 2 Func, 2500ohm, 3-wire Serial Control Interface, 64 Positions, PBGA24, CSP, BGA-24

器件类别:模拟混合信号IC    转换器   

厂商名称:Catalyst

厂商官网:http://www.catalyst-semiconductor.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Catalyst
零件包装代码
BGA
包装说明
VFBGA, BGA24,4X6,20
针数
24
Reach Compliance Code
unknown
ECCN代码
EAR99
其他特性
NONVOLATILE MEMORY
控制接口
3-WIRE SERIAL
转换器类型
DIGITAL POTENTIOMETER
JESD-30 代码
R-PBGA-B24
JESD-609代码
e0
功能数量
2
位置数
64
端子数量
24
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
VFBGA
封装等效代码
BGA24,4X6,20
封装形状
RECTANGULAR
封装形式
GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)
240
电源
3/5 V
认证状态
Not Qualified
电阻定律
LINEAR
最大电阻容差
20%
最大电阻器端电压
3 V
最小电阻器端电压
座面最大高度
0.765 mm
标称供电电压
3 V
表面贴装
YES
标称温度系数
300 ppm/°C
温度等级
COMMERCIAL
端子面层
TIN LEAD
端子形式
BALL
端子节距
0.5 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
30
标称总电阻
2500 Ω
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Preliminary Information
CAT5411
Dual Digitally Programmable Potentiometers (DPP™) with
64 Taps and SPI Interface
FEATURES
s
Two linear-taper digitally programmable
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Automatic recall of saved wiper settings at
potentiometers
s
64 resistor taps per potentiometer
s
End to end resistance 2.5k
, 10k
, 50k
or 100k
s
Potentiometer control and memory access via
power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
µ
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
24-lead SOIC, 24-lead TSSOP, and BGA
s
Commercial and industrial temperature ranges
SPI interface: Mode (0, 0) and (1, 1)
s
Low wiper resistance, typically 50Ω
s
Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
two potentiometers is automatically loaded into its
respective wiper control register.
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges and offered in a 24-lead SOIC and TSSOP
package or in the chip scale BGA.
PIN CONFIGURATION
SOIC Package (J, W)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5411
18
17
16
15
14
13
1
A
B
RW0
RL0
VCC
NC
NC
NC
NC
NC
NC
NC
A0
SO
HOLD
SCK
NC
NC
NC
NC
2
CS
WP
RH0
NC
SO
A0
SI
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCK
HOLD
3
A1
SI
RH1
NC
HOLD
SCK
TSSOP Package (U, Y)
1
2
3
4
5
6
7
8
9
10
11
12
4
RL1
RW1
VSS
NC
NC
NC
24
23
22
21
20
CAT
19
5411
18
17
16
15
14
13
WP
CS
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
SO
FUNCTIONAL DIAGRAM
RH0
RH1
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R W0
R W1
WP
A0
A1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0
RL1
BGA
C
D
E
F
Top View - Bump Side Down
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2114, Rev. F
1
CAT5411
Preliminary Information
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN DESCRIPTIONS
Function
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Hold
Serial Data Output
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Pin
Pin
(TSSOP) (BGA) Name
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C1
B1
C2
A1
A2
B2
B3
A3
A4
C3
B4
C4
D4
E4
D3
F4
F3
E3
E2
F2
F1
D2
E1
D1
VCC
R
L0
R
H0
R
W0
CS
WP
SI
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCK
HOLD
SO
A0
NC
NC
NC
NC
SI:
Serial Input
SI is the serial data input pin. This pin is used to input
all opcodes, byte addresses and data to be written to
the CAT5411. Input data is latched on the rising edge
of the serial clock.
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5411. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5411. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when address-
ing multiple devices. When these pins are left floating
the default values are zero. A total of four devices
can be addressed on a single bus. A match in the
slave address must be made with the address input
in order to initiate communication with the CAT5411.
R
H
, R
L
: Resistor End Points
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
:
Wiper
The R
W
pins are equivalent to the wiper terminal of a
mechanical potentiometer.
CS:
Chip Select
CS
CS
is the Chip select pin.
CS
low enables the
CAT5411 and
CS
high disables the CAT5411.
CS
high takes the SO output pin to high impedance and forces the devices into a
Standby mode (unless an internal write operation is underway). The CAT5411 draws ZERO current in the Standby mode. A high
to low transition on
CS
is required prior to any sequence being initiated. A low to high transition on
CS
after a valid write sequence
is what initiates an internal write cycle.
Write Protect
WP:
WP
WP
is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
WP
is tied low, all
write operations to the wiper control and Data registers are inhibited.
WP
going low while
CS
is still low will interrupt a write to the
registers. If the internal write cycle has already been initiated,
WP
going low will have no effect on any write operation.
HOLD:
HOLD
Hold
The
HOLD
pin is used to pause transmission to the CAT5411 while in the middle of a serial sequence without having to re-
transmit entire sequence at a later time. To pause,
HOLD
must be brought low while SCK is low. The SO pin is in a high imped-
ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.)
HOLD
may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2114, Rev. F
2
Preliminary Information
CAT5411
SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5411 to interface directly with many
of today's popular microcontrollers. The CAT5041
contains an 8-bit instruction register .The instruction set
and the operation codes are detailed in the instruction
set table 3.
After the device is selected with
CS
going low the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK. The
first byte contains one of the six op-codes that define the
operation to be performed.
DEVICE OPERATION
The CAT5411 is two resistor arrays integrated with SPI
serial interface logic, four 6-bit wiper control registers
and eight 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
). R
H
and R
L
are
symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (R
W
) by a
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
3
Document No. 2114, Rev. F
CAT5411
Preliminary Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)
................... -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current .................................................. +12mA
Note:
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device perfor-
mance and reliability.
Recommended Operating Conditions:
V
CC
= +2.5V to +6.0V
Temperature
Commercial
Industrial
Min
0°C
-40°C
Max
70°C
85°C
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(3)
Relative Linearity
(4)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
R
ISO
fc
Temperature Coefficient of
R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Isolation Resistance
Frequency Response
R
POT
= 50kΩ
10/10/25
TBD
0.4
R
w(n)(actual)
-R
(n)(expected)(6)
R
w(n+1)
-[R
w(n)+LSB
]
(6)
+300
20
1.6
+1
+0.2
I
W
= +3mA @ V
CC
=3V
I
W
= +3mA @ V
CC
= 5V
V
SS
= 0V
GND
80
25°C, each pot
1
50
+6
300
150
V
CC
%
mW
mA
V
nV/ Hz
%
LSB
(5)
LSB
(5)
ppm/°C
ppm/°C
pF
MHz
Test Conditions
Min
Typ
100
50
10
2.5
+20
Max
Units
kΩ
kΩ
kΩ
kΩ
%
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(3) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(4) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(5) MI = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(6) n = 0, 1, 2, ..., 63
Document No. 2114, Rev. F
4
Preliminary Information
CAT5411
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Test Conditions
f
SCK
= 2MHz, SO Open
Inputs = GND
V
IN
= GND or V
CC;
SO Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
Max
1
1
10
10
Units
mA
µA
µA
µA
V
V
V
-1
V
CC
x 0.7
I
OL
= 3 mA
V
CC
x 0.3
V
CC
+ 1.0
0.4
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Min
Typ
Max
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
5
Document No. 2114, Rev. F
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参数对比
与CAT5411B-25-TE13相近的元器件有:CAT5411U-50-TE13、CAT5411J-50-TE13、CAT5411J-10-TE13、CAT5411W-00-TE13。描述及对比如下:
型号 CAT5411B-25-TE13 CAT5411U-50-TE13 CAT5411J-50-TE13 CAT5411J-10-TE13 CAT5411W-00-TE13
描述 Digital Potentiometer, 2 Func, 2500ohm, 3-wire Serial Control Interface, 64 Positions, PBGA24, CSP, BGA-24 Digital Potentiometer, 2 Func, 50000ohm, 3-wire Serial Control Interface, 64 Positions, PDSO24, TSSOP-24 Digital Potentiometer, 2 Func, 50000ohm, 3-wire Serial Control Interface, 64 Positions, PDSO24, 0.300 INCH, SOIC-24 Digital Potentiometer, 2 Func, 10000ohm, 3-wire Serial Control Interface, 64 Positions, PDSO24, 0.300 INCH, SOIC-24 Digital Potentiometer, 2 Func, 100000ohm, 3-wire Serial Control Interface, 64 Positions, PDSO24, 0.300 INCH, SOIC-24
是否Rohs认证 不符合 不符合 不符合 不符合 符合
厂商名称 Catalyst Catalyst Catalyst Catalyst Catalyst
零件包装代码 BGA TSSOP SOIC SOIC SOIC
包装说明 VFBGA, BGA24,4X6,20 LSSOP, TSSOP24,.25 SOP, SOP24,.4 SOP, SOP24,.4 SOP, SOP24,.4
针数 24 24 24 24 24
Reach Compliance Code unknown unknown unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99
其他特性 NONVOLATILE MEMORY NONVOLATILE MEMORY NONVOLATILE MEMORY NONVOLATILE MEMORY NONVOLATILE MEMORY
控制接口 3-WIRE SERIAL 3-WIRE SERIAL 3-WIRE SERIAL 3-WIRE SERIAL 3-WIRE SERIAL
转换器类型 DIGITAL POTENTIOMETER DIGITAL POTENTIOMETER DIGITAL POTENTIOMETER DIGITAL POTENTIOMETER DIGITAL POTENTIOMETER
JESD-30 代码 R-PBGA-B24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24
JESD-609代码 e0 e0 e0 e0 e3
功能数量 2 2 2 2 2
位置数 64 64 64 64 64
端子数量 24 24 24 24 24
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 VFBGA LSSOP SOP SOP SOP
封装等效代码 BGA24,4X6,20 TSSOP24,.25 SOP24,.4 SOP24,.4 SOP24,.4
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY, VERY THIN PROFILE, FINE PITCH SMALL OUTLINE, LOW PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
峰值回流温度(摄氏度) 240 240 240 240 260
电源 3/5 V 3/5 V 3/5 V 3/5 V 3/5 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
电阻定律 LINEAR LINEAR LINEAR LINEAR LINEAR
最大电阻容差 20% 20% 20% 20% 20%
最大电阻器端电压 3 V 3 V 3 V 3 V 3 V
座面最大高度 0.765 mm 1.25 mm 2.65 mm 2.65 mm 2.65 mm
标称供电电压 3 V 3 V 3 V 3 V 3 V
表面贴装 YES YES YES YES YES
标称温度系数 300 ppm/°C 300 ppm/°C 300 ppm/°C 300 ppm/°C 300 ppm/°C
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 TIN LEAD TIN LEAD TIN LEAD TIN LEAD MATTE TIN
端子形式 BALL GULL WING GULL WING GULL WING GULL WING
端子节距 0.5 mm 0.65 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 BOTTOM DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 30 30 30 40
标称总电阻 2500 Ω 50000 Ω 50000 Ω 10000 Ω 100000 Ω
长度 - 7.8 mm 15.4 mm 15.4 mm 15.4 mm
湿度敏感等级 - 1 1 1 1
宽度 - 4.4 mm 7.5 mm 7.5 mm 7.5 mm
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