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CD40108BFMSR

4X4 MULTI-PORT SRAM, 972ns, CDIP24, FRIT SEALED, DIP-24

器件类别:存储    存储   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
厂商名称
Renesas(瑞萨电子)
零件包装代码
DIP
包装说明
DIP,
针数
24
Reach Compliance Code
unknown
ECCN代码
3A001.A.2.C
最长访问时间
972 ns
JESD-30 代码
R-GDIP-T24
JESD-609代码
e0
内存密度
16 bit
内存集成电路类型
MULTI-PORT SRAM
内存宽度
4
功能数量
1
端子数量
24
字数
4 words
字数代码
4
工作模式
SYNCHRONOUS
最高工作温度
125 °C
最低工作温度
-55 °C
组织
4X4
封装主体材料
CERAMIC, GLASS-SEALED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
并行/串行
PARALLEL
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class V
座面最大高度
5.72 mm
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
TIN LEAD
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
总剂量
100k Rad(Si) V
宽度
15.24 mm
文档预览
CD40108BMS
December 1992
CMOS 4 x 4 Multiport Register
Description
The CD40108BMS is a 4 x 4 multiport register containing
four 4-bit registers, write address decoder, two separate
read address decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output
bus is switched, independently of the clock, to a high-imped-
ance state. The high-impedance third state provides the out-
puts with the capability of being connected to the bus lines in
a bus-organized system without the need for interface or
pull-up components.
When the WRITE ENABLE input is high, all data input lines
are latched on the positive transition of the CLOCK and the
data is entered into the word selected by the write address
lines. When WRITE ENABLE is low, the CLOCK is inhibited
and no new data is entered. In either case, the contents of
any word may be accessed via the read address lines inde-
pendent of the state of the CLOCK input.
The CD40108BMS is supplied in these 24-lead outline pack-
ages:
Braze Seal DIP
Ceramic Flatpack
H4V
H4P
Features
• High Voltage Type (20V Rating)
• Four 4-Bit Registers
• One Input and Two Output Buses
• Unlimited Expansion in Bit and Word Directions
• Data Lines have latched Inputs
• 3-State Outputs
• Separate Control of Each Bus, Allowing Simultaneous
Independent Reading of Any of Four Registers on Bus
A and Bus B and Independent Writing Into Any of the
Four Registers
• CD40108BMS is Pin-Compatible with Industry Type
MC14580
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Scratch-Pad Memories
• Arithmetic Units
• Data Storage
Pinout
CD40108BMS
TOP VIEW
Q3 B 1
Q2 B 2
3-STATE A 3
Q0 A 4
Q1 A 5
Q2 A 6
Q3 A 7
WRITE 0 8
WRITE 1 9
READ 1B 10
READ 0B 11
VSS 12
24 VDD
23 Q1 B
22 Q0 B
21 3-STATE B
20 D0
19 D1
18 D2
17 D3
16 CLOCK
15 WRITE ENABLE
14 READ 1A
13 READ 0A
Functional Diagram
WRITE
ENABLE
D0
DATA
INPUTS
D1
D2
D3
WRITE 0
WRITE 1
READ 1A
READ 0A
READ 1B
READ 0B
VDD = 24
VSS = 12
20
19
18
17
8
9
14
13
10
11
16
CLOCK
21
3-STATE B
22
23
2
1
Q0
Q1
Q2
Q3
WORD B
OUTPUT
3-STATE A
15
3
4
5
6
7
Q0
Q1
Q2
Q3
WORD A
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3356
7-25
Specifications CD40108BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
o
C/W
o
C/W
Ceramic DIP and FRIT Package . . . . . 80
20
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For T
A
= -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For T
A
= +100
o
C to +125
o
C (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For T
A
= Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Tri-State Output
Leakage
VIL
VIH
VIL
VIH
IOZL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIN = VDD or GND
VOUT = 0V
VDD = 20V
VDD = 18V
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3
1
2
3
1
2
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
3
1
2
3
+25
o
C,
LIMITS
TEMPERATURE
+25
o
C
+125 C
-55
o
C
+25
o
C
+125 C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+125
o
C,
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
-
3.5
-
11
-0.4
-12
-0.4
-
-
-
1.5
-
4
-
-
-
-
0.4
12
0.4
V
V
V
V
µA
µA
µA
µA
µA
µA
-55
o
C
o
o
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
MIN
-
-
-
-100
-1000
-100
-
-
-
-
14.95
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
VOH > VOL <
VDD/2 VDD/2
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-26
Specifications CD40108BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-
-
-
-
-
-
-
1.5
1.11
MAX
720
972
600
810
200
270
260
351
200
270
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay Clock
or Write Enable to Q
Propagation Delay Read
or Write Address to Q
Propagation Delay 3-
State Disable Delay Time
Propagation Delay 3-
State Disable Delay Time
Transition Time
SYMBOL
TPHL1
TPLH1
TPHL2
TPLH2
TPZH
TPHZ
TPZL
TPLZ
TTHL
TTLH
FCL
CONDITIONS
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
Maximum Clock Input
Frequency
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-55
o
C
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
50
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
MIN
-
-
-
-
-
-
-
MAX
5
150
10
300
10
600
50
UNITS
µA
µA
µA
µA
µA
µA
mV
7-27
Specifications CD40108BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH10
CONDITIONS
VDD = 10V, VOUT = 9.5V
NOTES
1, 2
TEMPERATURE
+125
o
C
-55
o
C
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Clock or Write Enable to Q
Propagation Delay
Read or Write Address to Q
Propagation Delay
3-State Disable Delay
Time
Propagation Delay
3-State Disable Delay
Time
Transition Time
VIL
VIH
TPLH1
TPHL1
TPHL2
TPLH2
TPZH
TPHZ
TPZL
TPLZ
TTLH
TTHL
FCL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TS
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Data Setup
Time
Write Enable to Clock
Minimum Data Setup
Time
Write Address to Clock
Clock Rise and Fall Time
TS
VDD = 5V
VDD = 10V
VDD = 15V
TS
VDD = 5V
VDD = 10V
VDD = 15V
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Hold Time Data
to Clock
TH
VDD = 5V
VDD = 10V
VDD = 15V
Hold Time Write Enable
to Clock
TH
VDD = 5V
VDD = 10V
VDD = 15V
Write Address to Clock
TH
VDD = 5V
VDD = 10V
VDD = 15V
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3, 5
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
3.5
4.5
0
0
0
250
100
70
250
100
70
-
-
-
220
100
80
-
-
-
-
-
-
270
130
80
330
140
90
15
5
5
MAX
-0.9
-1.6
-2.4
-4.2
3
-
280
200
240
170
100
80
120
100
100
80
-
-
UNITS
mA
mA
mA
mA
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Maximum Clock Input
Frequency
Minimum Data Setup
Time
Data to Clock
7-28
Specifications CD40108BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Minimum Clock Pulse
Width Clock or Write
Enable
Minimum Clock Pulse
Width Write Address
SYMBOL
TW
CONDITIONS
VDD = 5V
VDD = 10V
VDD = 15V
TW
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
CIN
Any Input
NOTES
3
3
3
3
3
3
1, 2
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
-
-
-
-
MAX
350
130
90
300
150
90
7.5
UNITS
ns
ns
ns
ns
ns
ns
pF
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
IDD
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
µA
V
V
V
V
V
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
o
C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
±
1.0µA
±
20% x Pre-Test Reading
±
20% x Pre-Test Reading
DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
MIL-STD-883
METHOD
100% 5004
GROUP A SUBGROUPS
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
7-29
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参数对比
与CD40108BFMSR相近的元器件有:CD40108BDMSR、CD40108BKMSR、CD40108BHMSR。描述及对比如下:
型号 CD40108BFMSR CD40108BDMSR CD40108BKMSR CD40108BHMSR
描述 4X4 MULTI-PORT SRAM, 972ns, CDIP24, FRIT SEALED, DIP-24 4X4 DUAL-PORT SRAM, 972ns, CDIP24, CERAMIC, DIP-24 4X4 DUAL-PORT SRAM, 972ns, CDFP24, CERAMIC, FP-24 4X4 DUAL-PORT SRAM, 972ns, UUC24, DIE-24
零件包装代码 DIP DIP DFP DIE
包装说明 DIP, DIP, DIP24,.4 DFP, FL24,.4 DIE,
针数 24 24 24 24
Reach Compliance Code unknown not_compliant not_compliant compliant
ECCN代码 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C
最长访问时间 972 ns 972 ns 972 ns 972 ns
JESD-30 代码 R-GDIP-T24 R-CDIP-T24 R-CDFP-F24 R-XUUC-N24
内存密度 16 bit 16 bit 16 bit 16 bit
内存集成电路类型 MULTI-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM
内存宽度 4 4 4 4
功能数量 1 1 1 1
端子数量 24 24 24 24
字数 4 words 4 words 4 words 4 words
字数代码 4 4 4 4
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C
组织 4X4 4X4 4X4 4X4
封装主体材料 CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED UNSPECIFIED
封装代码 DIP DIP DFP DIE
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE IN-LINE FLATPACK UNCASED CHIP
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V
表面贴装 NO NO YES YES
技术 CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY
端子形式 THROUGH-HOLE THROUGH-HOLE FLAT NO LEAD
端子位置 DUAL DUAL DUAL UPPER
总剂量 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
厂商名称 Renesas(瑞萨电子) - Renesas(瑞萨电子) Renesas(瑞萨电子)
JESD-609代码 e0 e0 e0 -
座面最大高度 5.72 mm 5.72 mm 2.92 mm -
端子面层 TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
端子节距 2.54 mm 2.54 mm 1.27 mm -
宽度 15.24 mm 15.24 mm 9.905 mm -
是否Rohs认证 - 不符合 不符合 不符合
峰值回流温度(摄氏度) - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
处于峰值回流温度下的最长时间 - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
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