CD4066BC Quad Bilateral Switch
November 1983
Revised October 2005
CD4066BC
Quad Bilateral Switch
General Description
The CD4066BC is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin-for-pin compatible with CD4016BC, but has a much
lower “ON” resistance, and “ON” resistance is relatively
constant over the input-signal range.
s
High degree linearity
High degree linearity
High degree linearity
s
Extremely low “OFF”
0.1% distortion (typ.)
@ f
is
=
1 kHz, V
is
=
5V
p-p
,
V
DD
−
V
SS
=
10V, R
L
=
10 k
Ω
0.1 nA (typ.)
10
12
Ω
(typ.)
switch leakage: @ V
DD
−
V
SS
=
10V, T
A
=
25
°
C
s
Extremely high control input impedance
s
Low crosstalk
Features
s
Wide supply voltage range
s
High noise immunity
analog switching
s
“ON” resistance for 15V operation 80
Ω
s
Matched “ON” resistance
over 15V signal input
s
“ON” resistance flat over peak-to-peak signal range
s
High “ON”/“OFF”
65 dB (typ.)
@ f
is
=
10 kHz, R
L
=
10 k
Ω
output voltage ratio
s
Control Line Biasing:
Switch On (Logic 1), V
C
=
V
DD
Switch Off (Logic 0), V
C
=
V
SS
s
Wide range of digital and
3V to 15V
0.45 V
DD
(typ.)
−
50 dB (typ.)
@ f
is
=
0.9 MHz, R
L
=
1 k
Ω
between switches
s
Frequency response, switch “ON” 40 MHz (typ.)
±
7.5 V
PEAK
Applications
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase, and
analog-signal-gain
∆
R
ON
=
5
Ω
(typ.)
Ordering Code:
Order Number
CD4066BCM
CD4066BCSJ
CD4066BCN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Schematic Diagram
© 2005 Fairchild Semiconductor Corporation
DS005665
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CD4066BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
300
°
C
(Note 2)
700 mW
500 mW
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
3V to 15V
0V to V
DD
−
0.5V to
+
18V
−
0.5V to V
CC
+
0.5V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
Note 2:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device Current
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
SIGNAL INPUTS AND OUTPUTS
R
ON
“ON” Resistance
Conditions
−55°C
Min
Max
0.25
0.5
1.0
Min
+25°C
Typ
0.01
0.01
0.01
Max
0.25
0.5
1.0
+125°C
Min
Max
7.5
15
30
Units
µA
R
L
=
10 kΩ to (V
DD
−
V
SS
/2)
V
C
=
V
DD
, V
SS
to V
DD
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
800
310
200
270
120
80
1050
400
240
1300
550
320
Ω
∆R
ON
∆“ON”
Resistance Between
Any 2 of 4 Switches
R
L
=
10 kΩ to (V
DD
−
V
SS
/2)
V
CC
=
V
DD
, V
IS
=
V
SS
to V
DD
V
DD
=
10V
V
DD
=
15V
10
5
±50
±0.1
±50
±500
Ω
nA
I
IS
Input or Output Leakage
Switch “OFF”
V
C
=
0
CONTROL INPUTS
V
ILC
LOW Level Input
Voltage
V
IS
=
V
SS
and V
DD
V
OS
=
V
DD
and V
SS
I
IS
= ±
10µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
IHC
HIGH Level Input
Voltage
I
IN
Input Current
V
DD
=
5V
V
DD
=
10V (Note 7)
V
DD
=
15V
V
DD
−V
SS
=
15V
V
DD
≥V
IS
≥V
SS
V
DD
≥V
C
≥V
SS
3.5
7.0
11.0
−0.1
0.1
1.5
3.0
4.0
3.5
7.0
11.0
2.25
4.5
6.75
2.75
5.5
8.25
−10
−
5
10
−
5
−0.1
0.1
1.5
3.0
4.0
3.5
7.0
11.0
−0.1
0.1
µA
V
1.5
3.0
4.0
V
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2
CD4066BC
AC Electrical Characteristics
Symbol
t
PHL
, t
PLH
Parameter
Propagation Delay Time Signal
Input to Signal Output
(Note 3)
Conditions
Min
Typ
Max
Units
T
A
=
25
°
C, t
r
=
t
f
=
20 ns and V
SS
=
0V unless otherwise noted
V
C
=
V
DD
, C
L
=
50 pF, (Figure 1)
R
L
=
200k
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
t
PZH
, t
PZL
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
t
PHZ
, t
PLZ
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Frequency Response-Switch
“ON” (Frequency at
−3
dB)
R
L
=
1.0 kΩ, C
L
=
50 pF, (Figure 2, Figure 3)
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
R
L
=
1.0 kΩ, C
L
=
50 pF, (Figure 2, Figure 3)
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
C
=
V
DD
=
5V, V
SS
= −5V
R
L
=
10 kΩ, V
IS
=
5V
p-p
, f= 1 kHz, (Figure 4)
V
C
=
V
DD
=
5V, V
SS
= −5V,
R
L
=
1 kΩ, V
IS
=
5V
p-p
,
20 Log
10
V
OS
/V
OS
(1 kHz)−dB,
(Figure 4)
Feedthrough — Switch “OFF”
(Frequency at
−50
dB)
Crosstalk Between Any Two
Switches (Frequency at
−50
dB)
Crosstalk; Control Input to
Signal Output
Maximum Control Input
V
DD
=
5.0V, V
CC
=
V
SS
= −5.0V,
R
L
=
1 kΩ, V
IS
=
5.0V
p-p
, 20 Log
10
,
V
OS
/V
IS
= −50
dB, (Figure 4)
V
DD
=
V
C(A)
=
5.0V; V
SS
=
V
C(B)
=
5.0V,
R
L
1 kΩ, V
IS(A)
=
5.0 V
p-p
, 20 Log
10
,
V
OS(B)
/V
IS(A)
= −50
dB (Figure 5)
V
DD
=
10V, R
L
=
10 kΩ, R
IN
=
1.0 kΩ,
V
CC
=
10V Square Wave, C
L
=
50 pF
(Figure 6)
R
L
=
1.0 kΩ, C
L
=
50 pF, (Figure 7)
V
OS(f)
=
½ V
OS
(1.0 kHz)
V
DD
=
5.0V
V
DD
=
10V
V
DD
=
15V
C
IS
C
OS
C
IOS
C
IN
Signal Input Capacitance
Signal Output Capacitance
Feedthrough Capacitance
Control Input Capacitance
V
DD
=
10V
V
C
=
0V
6.0
8.0
8.5
8.0
8.0
0.5
5.0
7.5
MHz
MHz
MHz
pF
pF
pF
pF
150
mV
p-p
0.9
MHz
1.25
40
MHz
0.1
125
60
50
ns
ns
ns
%
125
60
50
ns
ns
ns
25
15
10
55
35
25
ns
ns
ns
Note 3:
AC Parameters are guaranteed by DC correlated testing.
Note 4:
These devices should not be connected to circuits with the power “ON”.
Note 5:
In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in C
L
wherever it is
specified.
Note 6:
V
IS
is the voltage at the in/out pin and V
OS
is the voltage at the out/in pin. V
C
is the voltage at the control input.
Note 7:
Conditions for V
IHC
: a) V
IS
=
V
DD
, I
OS
=
standard B series I
OH
b) V
IS
=
0V, I
OL
=
standard B series I
OL
.
3
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CD4066BC
Typical Performance Characteristics
“ON” Resistance vs Signal
Voltage for T
A
=
25
°
C
“ON” Resistance as a Function
of Temperature for
V
DD
−
V
SS
=
15V
“ON” Resistance as a Function
of Temperature for
V
DD
−
V
SS
=
10V
“ON” Resistance as a Function
of Temperature for
V
DD
−
V
SS
=
5V
Special Considerations
In applications where separate power sources are used to
drive V
DD
and the signal input, the V
DD
current capability
should exceed V
DD
/R
L
(R
L
=
effective external load of the 4
CD4066BC bilateral switches). This provision avoids any
permanent current flow or clamp action of the V
DD
supply
when power is applied or removed from CD4066BC.
In certain applications, the external load-resistor current
may include both V
DD
and signal-line components. To
avoid drawing V
DD
current when switch current flows into
terminals 1, 4, 8 or 11, the voltage drop across the
bidirectional switch must not exceed 0.6V at T
A
≤
25
°
C, or
0.4V at T
A
>
25
°
C (calculated from R
ON
values shown).
No V
DD
current will flow through R
L
if the switch current
flows into terminals 2, 3, 9 or 10.
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4
CD4066BC
AC Test Circuits and Switching Time Waveforms
FIGURE 1. t
PHL
, t
PLH
Propagation Delay Time Signal Input to Signal Output
FIGURE 2. t
PZH
, t
PHZ
Propagation Delay Time Control to Signal Output
FIGURE 3. t
PZL
, t
PLZ
Propagation Delay Time Control to Signal Output
V
C
=
V
DD
for distortion and frequency response tests
V
C
=
V
SS
for feedthrough test
FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough
5
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