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CD4066BKMS

QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDFP14, CERAMIC, FP-14

器件类别:模拟混合信号IC    信号电路   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
厂商名称
Renesas(瑞萨电子)
零件包装代码
DFP
包装说明
DFP,
针数
14
Reach Compliance Code
compliant
模拟集成电路 - 其他类型
SPST
JESD-30 代码
R-CDFP-F14
JESD-609代码
e0
标称负供电电压 (Vsup)
信道数量
1
功能数量
4
端子数量
14
最大通态电阻 (Ron)
1300 Ω
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DFP
封装形状
RECTANGULAR
封装形式
FLATPACK
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class V
座面最大高度
2.92 mm
标称供电电压 (Vsup)
5 V
表面贴装
YES
最长断开时间
70 ns
最长接通时间
70 ns
技术
CMOS
温度等级
MILITARY
端子面层
TIN LEAD
端子形式
FLAT
端子节距
1.27 mm
端子位置
DUAL
宽度
6.285 mm
文档预览
CD4066BMS
December 1992
CMOS Quad Bilateral Switch
Description
CD4066BMS is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is
pin for pin compatible with CD4016B, but exhibits a much
lower on state resistance. In addition, the on-state resistance
is relatively constant over the full input signal range.
The CD4066BMS consists of four independent bilateral
switches. A single control signal is required per switch. Both
the p and the n device in a given switch are biased on or off
simultaneously by the control signal. As shown in Figure 1,
the well of the n channel device on each switch is either tied
to the input when the switch is on or to VSS when the switch
is off. This configuration eliminates the variation of the switch
transistor threshold voltage with input signal, and thus keeps
the on-state resistance low over the full operating signal
range.
The advantages over single channel switches include peak
input signal voltage swings equal to the full supply voltage,
and more constant on-state impedance over the input signal
range. For sample and hold applications, however, the
CD4016B is recommended.
The CD4066BMS is supplied in these 14-lead outline pack-
ages:
Braze Seal DIP
H4Q
Frit Seal DIP
H1B
Ceramic Flatpack H3W
Features
• For Transmission or Multiplexing of Analog or Digital
Signals
• High Voltage Types (20V Rating)
• 15V Digital or
±7.5V
Peak-to-Peak Switching
• 125Ω Typical On-State Resistance for 15V Operation
• Switch On-State Resistance Matched to Within 5Ω
Over 15V Signal Input Range
• On-State Resistance Flat Over Full Peak-to-Peak Sig-
nal Range
• High On/Off Output Voltage Ratio
- 80dB Typ. at FIS = 10kHz, RL = 1kΩ
• High Degree of Linearity: <0.5% Distortion Typ. at
FIS = 1kHz, VIS = 5Vp-p, VDD - VSS
10V, RL = 10kΩ
• Extremely Low Off-State Switch Leakage Resulting in
Very Low Offset Current and High Effective Off-State
Resistance: 10pA Typ. at VDD - VSS = 10V, T
A
= +25
o
C
• Extremely High Control Input Impedance (Control Cir-
cuit Isolated from Signal Circuit): 10
12
Typ.
• Low Crosstalk Between Switches: -50dB Typ. at FIS =
8MHz, RL = 1kΩ
• Matched
Control
Input
to
Signal
Output
Capacitance: Reduces Output Signal Transients
• Frequency Response, Switch on = 40MHz (Typ.)
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
“B” Series CMOS Devices”
Pinout
CD4066BMS
TOP VIEW
IN/OUT A 1
OUT/IN A 2
14 VDD
13 CONT A
12 CONT D
11 IN/OUT D
10 OUT/IN D
9 OUT/IN C
8 IN/OUT C
Applications
• Analog Signal Switching/Multiplexing
- Signal Gating
- Modulator
- Squelch Control
- Demodulator
- Chopper
- Commutating Switch
• Digital Signal Switching/Multiplexing
• Transmission Gate Logic Implementation
• Analog to Digital & Digital to Analog Conversion
• Digital Control of Frequency, Impedance, Phase, and
Analog Signal Gain
OUT/IN B 3
IN/OUT B 4
CONT B 5
CONT C 6
VSS 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3319
7-966
Specifications CD4066BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
Ceramic DIP and FRIT Package . . . . . 80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VC = VDD or GND
3
1
2
3
Input Leakage Current
IIH
VC = VDD or GND
1
2
3
Input/Output Leakage
Current (Switch OFF)
IOZL
VC = 0V, VIS = 18V,
VOS = 0V, VIS = 0V,
VOS = 18V
VDD = 20
1
2
VDD = 18V
IOZH
VDD = 20
3
1
2
VDD = 18V
On Resistance
RON5
RON10
RON15
On Resistance
RON5
VC = VDD, RL = 10kW VDD = 5V
returned to VDD -
VDD = 10V
VSS/2
VDD = 15V
VIS = VSS to VDD
VDD = 5V
3
1
1
1
1, 2
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
On Resistance
RON10
VDD = 10V
1, 2
+125
o
C
-55
o
C
On Resistance
RON15
VDD = 15V
1, 2
+125
o
C
-55
o
C
Functional
(Note 3)
F
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Switch Threshold
RL = 100k to VDD
N Threshold Voltage
P Threshold Voltage
SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND
SWTHRH15 VDD = 15V, VC = 2V, VIS = GND
VNTH
VPTH
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
7
7
8A
8B
1, 2, 3
1, 2, 3
1
1
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+25
o
C
4.1
14.1
-2.8
0.7
-
-
-0.7
2.8
V
V
V
V
MIN
-
-
-
-100
-1000
-100
-
-
-
-100
-1000
-100
-
-
-
1050
400
240
-
-
-
-
-
-
MAX
0.5
50
0.5
-
-
-
100
1000
100
-
-
-
100
1000
100
-
-
-
1300
800
550
310
320
220
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
V
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
VOH > VOL <
VDD/2 VDD/2
7-967
Specifications CD4066BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
MIN
-
-
MAX
1
2
UNITS
V
V
PARAMETER
Control Input Low
Voltage (Note 2)
|IIS| < 10µa, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
Control Input High
Voltage
(Note 2, Figure 2)
VIS = VSS and VIS =
VDD
SYMBOL
VILC5
VILC15
CONDITIONS
(NOTE 1)
VDD = 5V
VDD = 15V
VIHC
VDD = 5V, |IIS| = .51mA, 4.6V <
VOS < 0.4V
VDD = 5V, |IIS| = .36mA, 4.6V <
VOS < 0.4V
VDD = 5V, |IIS| = .64mA, 4.6V <
VOS < 0.4V
1
2
3
1
2
3
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
3.5
3.5
3.5
11
11
11
-
-
-
-
-
-
V
V
V
V
V
V
VIHC
VDD = 15V, |IIS| = 3.4mA, 13.5V <
VOS <1.5V
VDD = 15V, |IIS| = 2.4mA, 13.5V <
VOS < 1.5V
VDD = 15V, |IIS| = 4.2mA, 13.5V <
VOS <1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. VDD = 2.8V/3.0V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-
MAX
40
54
70
95
UNITS
ns
ns
ns
ns
PARAMETER
Propagation Delay
Signal Input to Signal
Output
Propagation Delay
Turn-On, Turn-Off
NOTES:
SYMBOL
TPLH
TPHL
CONDITIONS
VC = VDD = 5V, VSS = GND
(Notes 2, 3)
TPHZ/ZH VIS = VDD = 5V (Notes 1, 2)
TPLZ/ZL
1. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Control Input Low
Voltage
|IIS| < 10µa, VIS = VSS,
VOS = VDD and
VIS = VDD, VOS = VSS
VILC10
VDD = 10V
1, 2
+25
o
C, +125
o
C,
-55
o
C
MIN
-
-
-
-
-
-
-
MAX
0.25
7.5
0.5
15
0.5
30
2
UNITS
µA
µA
µA
µA
µA
µA
V
7-968
Specifications CD4066BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Control Input High
Voltage (See Figure 2)
Propagation Delay
Signal Input to
Signal Output
Propagation Delay
Turn-On, Turn-Off
Input Capacitance
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
IDD
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
µA
V
V
V
V
V
SYMBOL
VIHC10
TPLH
TPHL
CONDITIONS
VDD = 10V, VIS = VDD or GND
VDD = 10V
VDD = 15V
NOTES
2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
7
-
-
-
-
-
MAX
-
20
15
40
30
7.5
UNITS
V
ns
ns
ns
ns
pF
TPHZ/ZH VDD = 10V
TPLZ/ZL
VDD = 15V
CIN
Any Input
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
Supply Current - SSI
ON Resistance
SYMBOL
IDD
RONDEL10
±0.1µA
±
20% x Pre-Test Reading
DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
MIL-STD-883
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
IDD, IOL5, IOH5A, RONDEL10
READ AND RECORD
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
7-969
Specifications CD4066BMS
TABLE 6. APPLICABLE SUBGROUPS
(Continued)
CONFORMANCE GROUP
Final Test
Group A
Group B
Subgroup B-5
Subgroup B-6
Group D
MIL-STD-883
METHOD
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
Subgroups 1, 2, 3, 9, 10, 11
READ AND RECORD
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
5005
TEST
PRE-IRRAD
1, 7, 9
POST-IRRAD
Table 4
READ AND RECORD
PRE-IRRAD
1, 9
POST-IRRAD
Table 4
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1 (Note 1)
Static Burn-In 2 (Note 1)
Dynamic Burn-In (Note 1)
Irradiation (Note 2)
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
±
5%, VDD = 18V
±
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
±
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V
±
0.5V
OPEN
2, 3, 9, 10
2, 3, 9, 10
-
2, 3, 9, 10
GROUND
1, 4-8, 11-13
7
7
7
VDD
14
1, 4-6, 8, 11-14
14
1, 4-6, 8, 11-14
2, 3, 9, 10
5, 6, 12, 13
1, 4, 8, 11
9V
±
-0.5V
50kHz
25kHz
Functional Diagram
TRUTH TABLE EACH SWITCH
IN/OUT
SIG A
OUT/IN
2
1
SW
A
13
CONTROL A
14
VDD
INPUT
VC
1
1
VIS
0
1
0
1
OUTPUT
VOS
0
1
Open
Open
OUT/IN
SIG B
IN/OUT
3
SW
D
12
CONTROL D
0
0
4
SW
B
11
IN/OUT
SIG D
CONTROL B
5
10
OUT/IN
Positive Logic: Switch ON VC = “1”
Switch OFF VC = “0”
CONTROL C
6
SW
C
9
OUT/IN
SIG C
VSS
7
8
IN/OUT
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
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参数对比
与CD4066BKMS相近的元器件有:CD4066BFMS、CD4066BDMS。描述及对比如下:
型号 CD4066BKMS CD4066BFMS CD4066BDMS
描述 QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDFP14, CERAMIC, FP-14 QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP14, FRIT SEALED, DIP-14 QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP14, BRAZE SEALED, DIP-14
零件包装代码 DFP DIP DIP
包装说明 DFP, DIP, DIP,
针数 14 14 14
Reach Compliance Code compliant compliant compliant
模拟集成电路 - 其他类型 SPST SPST SPST
JESD-30 代码 R-CDFP-F14 R-GDIP-T14 R-CDIP-T14
JESD-609代码 e0 e0 e0
信道数量 1 1 1
功能数量 4 4 4
端子数量 14 14 14
最大通态电阻 (Ron) 1300 Ω 1300 Ω 1300 Ω
最高工作温度 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED
封装代码 DFP DIP DIP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 FLATPACK IN-LINE IN-LINE
认证状态 Not Qualified Not Qualified Not Qualified
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
座面最大高度 2.92 mm 5.08 mm 5.08 mm
标称供电电压 (Vsup) 5 V 5 V 5 V
表面贴装 YES NO NO
最长断开时间 70 ns 70 ns 70 ns
最长接通时间 70 ns 70 ns 70 ns
技术 CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY
端子面层 TIN LEAD TIN LEAD TIN LEAD
端子形式 FLAT THROUGH-HOLE THROUGH-HOLE
端子节距 1.27 mm 2.54 mm 2.54 mm
端子位置 DUAL DUAL DUAL
宽度 6.285 mm 7.62 mm 7.62 mm
Base Number Matches - 1 1
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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