CD4514BM CD4514BC CD4515BM CD4515BC 4-Bit Latched 4-to-16 Line Decoders
February 1988
CD4514BM CD4514BC CD4515BM CD4515BC
4-Bit Latched 4-to-16 Line Decoders
General Description
The CD4514B and CD4515B are 4-to-16 line decoders with
latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel en-
hancement mode transistors These circuits are primarily
used in decoding applications where low power dissipation
and or high noise immunity is required
The CD4514B (output active high option) presents a logical
‘‘1’’ at the selected output whereas the CD4515B presents
a logical ‘‘0’’ at the selected output The input latches are
R –S type flip-flops which hold the last input data presented
prior to the strobe transition from ‘‘1’’ to ‘‘0’’ This input data
is decoded and the corresponding output is activated An
output inhibit line is also available
Features
Y
Y
Y
Y
Wide supply voltage range
High noise immunity
Low power TTL
compatibility
Low quiescent power dissipation
3 0V to 15V
0 45 V
DD
(typ )
fan out of 2
driving 74L
0 025
mW
package
5 0 V
DC
Y
Y
Y
Single supply operation
Input impedance
e
10
12
X
typically
Plug-in replacement for MC14514 MC14515
Logic and Connection Diagrams
TL F 5994 – 1
Dual-In-Line Package
Order Number CD4514B or CD4515B
TL F 5994 – 2
Top View
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 5994
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1 and 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering 10 seconds)
b
0 5V to
a
18V
b
0 5V to V
DD
a
0 5V
b
65 C to
a
150 C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
CD4514BM CD4515BM
CD4514BC CD4515BC
3V to 15V
0V to V
DD
b
55 C to
a
125 C
b
40 C to
a
85 C
700 mW
500 mW
260 C
CD4515BM (Note 2)
b
55 C
a
25 C
a
125 C
DC Electrical Characteristics
CD4514BM
Symbol
I
DD
Parameter
Quiescent Device
Current
Low Level
Output Voltage
Conditions
V
DD
e
5V V
IN
e
V
DD
or V
SS
V
DD
e
10V V
IN
e
V
DD
or V
SS
V
DD
e
15V V
IN
e
V
DD
or V
SS
V
IH
e
V
DD
l
I
O
l
k
1
mA
V
DD
e
5V V
IL
e
0V
V
DD
e
10V
V
DD
e
15V
V
IH
e
V
DD
l
I
O
l
k
1
mA
V
DD
e
5V V
IL
e
0V
V
DD
e
10V
V
DD
e
15V
V
O
e
0 5V or 4 5V
V
DD
e
5V
l
I
O
l
k
1
mA
V
DD
e
10V V
O
e
1 0V or 9 0V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
O
e
0 5V or 4 5V
V
DD
e
5V
l
I
O
l
k
1
mA
V
DD
e
10V V
O
e
1 0V or 9 0V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
DD
e
5V V
O
e
0 4V
V
DD
e
10V V
O
e
0 5V
V
DD
e
15V V
O
e
1 5V
V
DD
e
5V V
O
e
4 6V
V
DD
e
10V V
O
e
9 5V
V
DD
e
15V V
O
e
13 5V
V
DD
e
15V V
IN
e
0V
V
DD
e
15V V
IN
e
15V
Units
mA
mA
mA
V
V
V
V
V
V
Min
Max
5
10
20
0 05
0 05
0 05
Min
Typ
0 005
0 010
0 015
0
0
0
Max
5
10
20
0 05
0 05
0 05
Min
Max
150
300
600
0 05
0 05
0 05
V
OL
V
OH
High Level
Output Voltage
4 95
9 95
14 95
15
30
40
35
70
11 0
0 64
16
42
b
0 64
b
1 6
b
4 2
b
0 1
4 95
9 95
14 95
5
10
15
2 25
4 50
6 75
15
30
40
4 95
9 95
14 95
15
30
40
35
70
11 0
0 36
0 90
2 40
b
0 36
b
0 90
b
2 40
b
0 1
b
1 0
V
IL
Low Level
Input Voltage
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
IH
High Level
Input Voltage
35
70
11 0
0 51
13
34
b
0 51
b
1 3
b
3 4
2 75
5 50
8 25
0 88
2 25
8 80
b
0 88
b
2 25
b
8 80
b
10
b
5
I
OL
Low Level Output
Current (Note 3)
High Level Output
Current (Note 3)
Input Current
I
OH
I
IN
01
10
b
5
01
10
mA
mA
DC Electrical Characteristics
CD4514BC
Symbol
I
DD
Parameter
Quiescent Device
Current
Low Level
Output Voltage
Conditions
CD4515BC (Note 2)
b
40 C
a
25 C
a
85 C
Units
mA
mA
mA
Min
V
DD
e
5V V
IN
e
V
DD
or V
SS
V
DD
e
10V V
IN
e
V
DD
or V
SS
V
DD
e
15V V
IN
e
V
DD
or V
SS
V
IL
e
0V V
IH
e
V
DD
l
I
O
l
k
1
mA
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
IL
e
0V V
IH
e
V
DD
l
I
O
l
k
1
mA
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
2
Max
20
40
80
Min
Typ
0 005
0 010
0 015
Max
20
40
80
Min
Max
150
300
600
V
OL
0 05
0 05
0 05
0
0
0
0 05
0 05
0 05
0 05
0 05
0 05
V
V
V
V
OH
High Level
Output Voltage
4 95
9 95
14 95
4 95
9 95
14 95
50
10 0
15 0
4 95
9 95
14 95
V
V
V
DC Electrical Characteristics
CD4514BC
Symbol
V
IL
Parameter
Low Level
Input Voltage
Conditions
CD4515BC (Note 2) (Continued)
b
40 C
a
25 C
a
85 C
Units
Min
Max
15
30
40
Min
Typ
2 25
4 50
6 75
Max
15
30
40
Min
Max
15
30
40
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
b
1 0
l
I
O
l
k
1
mA
V
DD
e
5V V
O
e
0 5V or 4 5V
V
DD
e
10V V
O
e
1 0V or 9 0V
V
DD
e
15V V
O
e
1 5V or 13 5V
l
I
O
l
k
1
mA
V
DD
e
5V V
O
e
0 5V or 4 5V
V
DD
e
10V V
O
e
1 0V or 9 0V
V
DD
e
15V V
O
e
1 5V or 13 5V
V
DD
e
5V V
O
e
0 4V
V
DD
e
10V V
O
e
0 5V
V
DD
e
15V V
O
e
1 5V
V
DD
e
5V V
O
e
4 6V
V
DD
e
10V V
O
e
9 5V
V
DD
e
15V V
O
e
13 5V
V
DD
e
15V V
IN
e
0V
V
DD
e
15V V
IN
e
15V
35
70
11 0
0 52
13
36
b
0 52
b
1 3
b
3 6
V
IH
High Level
Input Voltage
35
70
11 0
0 44
11
30
b
0 44
b
1 1
b
3 0
b
0 3
2 75
5 50
8 25
0 88
2 25
88
b
0 88
b
2 25
b
8 8
b
10
b
5
b
0 3
35
70
11 0
0 36
0 90
24
b
0 36
b
0 90
b
2 4
I
OL
Low Level Output
Current (Note 3)
High Level Output
Current (Note 3)
Input Current
I
OH
I
IN
03
10
b
5
03
10
mA
mA
AC Electrical Characteristics
All types C
L
e
50 pF T
A
e
25 C t
r
e
t
f
e
20 ns unless otherwise specified
Symbol
t
THL
t
TLH
Parameter
Transition Times
Conditions
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
V
DD
e
5V
V
DD
e
10V
V
DD
e
15V
Per Package (Note 5)
Any Input (Note 4)
Min
Typ
100
50
40
550
225
150
400
150
100
125
50
38
175
50
38
150
5
75
Max
200
100
80
1100
450
300
800
300
200
250
100
75
350
100
75
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
t
PLH
t
PHL
Propagation Delay Times
t
PLH
t
PHL
Inhibit Propagation
Delay Times
Setup Time
t
SU
t
WH
Strobe Pulse Width
C
PD
C
IN
Power Dissipation Capacitance
Input Capacitance
AC Parameters are guaranteed by DC correlated testing
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteris-
tics’’ provide conditions for actual device operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
Note 4
Capacitance is guaranteed by periodic testing
Note 5
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C and 74C Family Characteristics application
note AN-90
3
Truth Table
Decode Truth Table (Strobe
e
1)
Data Inputs
Inhibit
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
e
Don’t Care
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Selected Output
CD4514
e
Logic ‘‘1’’
CD4515
e
Logic ‘‘0’’
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs
e
0 CD4514
All Outputs
e
1 CD4515
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
AC Test Circuit and Switching Time Waveforms
TL F 5994 – 4
TL F 5994 – 3
FIGURE 1
4
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch decoder to effect a complex data
routing system A total of 16 inputs from data registers are
selected and transferred via a TRI-STATE data bus to a
data distributor for rearrangement and entry into 16 output
registers In this way sequential data can be re-routed or
intermixed according to patterns determined by data select
and distribution inputs
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors One register is assigned to
each input The signals on A0 A1 and A2 choose 1-of-8
inputs for transfer out to the TRI-STATE data bus A fourth
signal labelled Dis disables one of the CD4512 selectors
assuring transfer of data from only one register
In addition to a choice of input registers 1–16 the rate of
transfer of the sequential information can also be varied
That is if the CD4512 were addressed at a rate that is
8 times faster than the shift frequency of the input registers
the most significant bit (MSB) from each register could be
selected for transfer to the data bus Therefore all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers
Information from the TRI-STATE bus is redistributed by the
CD4514B 4-bit latch decoder Using the 4-bit address
INA– IND the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers A–P This distribution of data bits to the output
registers can be made in many complex patterns For exam-
ple all of the most significant bits from the input registers
can be routed into output register A all of the next most
significant bits into register B etc In this way horizontal
vertical or other methods of data slicing can be implement-
