S E M I C O N D U C T O R
CD74FCT16511T,
CD74FCT162511T
Fast CMOS 16-Bit Registered/Latched
Transceiver with Parity
Description
Harris’ CD74FCT16511T and CD74FCT162511T are pro-
duced in an advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The CD74FCT16511T and CD74FCT162511T are high-
speed, low-power 16-bit registered/latched transceiver with
parity which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched or clocked modes. It
has a parity generator/checker in the A-to-B direction and a
parity checker in the B-to-A direction. Error checking is done
at the byte level with separate parity bits for each byte. One
error flag for each direction (A-to-B or B-to-A) exists to indi-
cate an error for either byte in either direction. The parity
error flags which are open drain outputs, can be tied
together and/or tied with flags from other devices to form a
single error flag or interrupt. To disable the error flag during
combinational transitions, a designer can disable the parity
error flag by the OEXX control pins.
The operation in A-to-B direction is controlled by LEAB,
CLKAB and OEAB control pins, and the operation in B-to-A
direction is controlled by LEBA, CLKBA and OEBA control
pins. GEN/CHK is used to select the operation of A-to-B
direction, while B-to-A direction is always in checking mode.
The ODD/EVEN select is common between the two direc-
tions. Independent operation can be achieved between the
two directions by using the corresponding control lines
except for the ODD/EVEN control.
December 1996
Features
• These Devices are High-speed, Low Power Devices
with High Current Drive
• V
CC
= 5V
±10%
• Hysteresis on All Inputs
• CD74FCT16511T
- High Output Drive: I
OH
= -32mA; I
OL
= 64mA
- Power Off Disable Outputs Permit "Live Insertion"
- Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
o
C
• CD74FCT162511T
- Balanced Output Drivers:
±24mA
- Open Drain Parity Error Allows Wire-OR
- Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
o
C
Pinout
CD74FCT16511T, CD74FCT162511T (SSOP, TSSOP)
TOP VIEW
OEAB
LEAB
PA
1
GND
A
0
A
1
V
CC
A
2
A
3
A
4
A
5
A
6
A
7
GND
PERA
A
8
A
9
A
10
A
11
A
12
A
13
V
CC
A
14
A
15
GND
PA
2
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GEN/CHK
CLKAB
PB
1
GND
B
0
B
1
V
CC
B
2
B
3
B
4
B
5
B
6
B
7
PERB
GND
B
8
B
9
B
10
B
11
B
12
B
13
V
CC
B
14
B
15
GND
PB
2
CLKBA
ODD/EVEN
Ordering Information
TEMP.
RANGE
(
o
C)
PKG.
NO.
M56.300-P
M56.300-P
M56.240-P
M56.300-P
M56.240-P
M56.300-P
PART NUMBER
CD74FCT16511ATSM
CD74FCT16511TSM
PACKAGE
-40 to 85 56 Ld SSOP
-40 to 85 56 Ld SSOP
CD74FCT162511ATMT -40 to 85 56 Ld TSSOP
CD74FCT162511ATSM -40 to 85 56 Ld SSOP
CD74FCT162511TMT
CD74FCT162511TSM
-40 to 85 56 Ld TSSOP
-40 to 85 56 Ld SSOP
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the varient in the tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
File Number
4218.2
1
CD74FCT16511T, CD74FCT162511T
Functional Block Diagram
ODD/EVEN
OEAB
LEBA
CLKBA
CLKAB
LEAB
C
D
C
A
0
-A
7
D
C
D
C
D
B
0
-B
7
OEBA
P
O
C
D
I
C
C
D
C
D
C
D
C
C
D
B
8
-B
15
PB
1
P
PA
1
C
D
D
A
8
-A
15
D
C
P
O
D
I
C
PA
2
C
D
C
PERA
(OPEN DRAIN)
D
D
C
D
C
D
C
D
C
D
P
PERB
(OPEN DRAIN)
PB
2
GEN/CHK
2
CD74FCT16511T, CD74FCT162511T
Simplified Functional Block Diagram
LEAB
CLKAB
DATA
16
PARITY
GEN/CHK
BYTE
PARITY
GENERATOR/
CHECKER
2
LATCH/
REGISTER
OEAB
PARITY, DATA
18
B
0-15
PB
1, 2
PERB
(OPEN DRAIN)
A
0-15
PA
1, 2
ODD/EVEN
LEBA
CLKBA
PARITY, DATA
18
PARITY, DATA
18
LATCH/
REGISTER
BYTE
PARITY
CHECKING
OEBA
PERA
(OPEN DRAIN)
TRUTH TABLE (NOTES 1 AND 2)
TRUTH TABLE
(NOTES 1, 2)
INPUTS
OUTPUT
BUFFERS
A
X
X
L
H
L
H
X
X
B
X
Z
L
H
L
H
B (Note 3)
B (Note 4)
TRUTH TABLE (PARITY GENERATION)
(NOTES 5, 6, 7, 8, 9)
TOTAL NUMBER OF INPUTS
THAT ARE HIGH, A
0
- A
7
ODD/EVEN
PB
1
1, 3, 5 or 7
L
H
1, 3, 5 or 7
H
L
0, 2, 4, 6 or 8
L
L
0, 2, 4, 6 or 8
H
H
NOTES:
5. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
6. A-to-B parity generation is shown. B-to-A can check parity while
A-to-B is performing generation. B-to-A will not generate parity.
7. The response shown is for LEAB = H. If LEAB = L, then CLKAB
will control as an edge triggered clock.
8. Conditions shown are for the byte A0-A7. The byte A8-A15 is
similar but will output the parity on PB2.
9. The error flag PERB will remain in a high state during parity gen-
eration.
TRUTH TABLE (PARITY CHECKING)
(NOTES 10, 11, 12, 13)
TOTAL NUMBER OF INPUTS THAT ARE
HIGH, A
0
- A
7
AND PA
1
(NOTE 14)
1, 3, 5, 7 or 9
1, 3, 5, 7 or 9
ODD/
EVEN
L
H
PB
1
L
H (Note 15)
OEAB
H
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
L
H
NOTES:
1. H = High Voltage Level
L = Low Voltage Level
X = Don’t Care or Irrelevant
Z = High Impedance
↑
= LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A flow control is the same, except
using OEBA, LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions
were established.
4. Output level before the indicated steady-state input conditions
were established, assuming CLKAB was HIGH before LEAB
went LOW.
0, 2, 4, 6 or 8
L
H (Note 15)
0, 2, 4, 6 or 8
H
L
10. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
11. A-to-B parity checking is shown. B-to-A parity checking is
same but uses OEBA = L, OEAB = H and errors will be indicat-
ed on PERA.
12. In parity checking mode the parity bits will be transmitted un-
changed along with the corresponding data regardless of par-
ity errors. (PB
1
= PA
1
)
13. The response shown is for LEAB = H. If LEAB = L, then CLK-
AB will control as an edge triggered clock.
14. Conditions shown are for the byte A
0
-A
7
and PA
1
. The byte
A
8
-A
15
and PA
2
is same.
15. The parity error flag PERB is a combined flag for both bytes A
0
-
A
7
and A
8
-A
15
. If a parity error occurs on either byte PERB will
go low.
3
CD74FCT16511T, CD74FCT162511T
Pin Descriptions
PIN NAME
OEAB
OEBA
CLKAB
CLKBA
LEAB
LEBA
PERA
PERB
A
X
B
X
ODD/EVEN
(Note 16)
GEN/CHK
(Note 16)
PA
X
(Note 17)
PB
X
GND
V
CC
NOTES:
16. ODD/EVEN and GEN/CHK should be tied to V
CC
or GND with
no resistor for optimum results.
17. The PA
X
pin input is internally disabled during parity generation.
This means that when generating parity in the A-to-B direction,
there is no need to add a pull-up resistor to guarantee state. The
pin will still function properly as the parity output for the B-to-A
direction.
DESCRIPTION
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Latch Enable Input
B-to-A Latch Enable Input
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or B-to-A 3-State Outputs
Parity Mode Selection Input
A-to-B Port Generate or Check Mode Input
A-to-B Parity Input, B-to-A Parity Output
B-to-A Parity Input, A-to-B Parity Output
Ground
Power
4
CD74FCT16511T, CD74FCT162511T
Absolute Maximum Ratings
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA
Thermal Information
Thermal Resistance (Typical, Note 18)
θ
JA
(
o
C/W)
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Supply Voltage to Ground Potential
Inputs and V
CC
Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
18.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS
SYMBOL
(NOTE 19)
TEST CONDITIONS
MIN
(NOTE 20)
TYP
MAX
UNITS
DC ELECTRICAL SPECIFICATIONS
Over the Operating Range, T
A
= -40
o
C to 85
o
C, V
CC
= 5.0V
±10%
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
(Input Pins)
Input HIGH Current
(I/O Pins)
Input LOW Current
(Input Pins)
Input LOW Current
(I/O Pins)
High Impedance
Output Current
Clamp Diode Voltage
Short Circuit Current
(I/O Pins)
Output Drive Current
(I/O Pins)
Output Leakage
Current (Open Drain)
Input Hysteresis
V
IH
V
IL
I
IH
I
IH
I
IL
I
IL
I
OZH
I
OZL
V
IK
I
OS
I
O
I
OFF
V
H
V
OH
V
CC
= Min, V
IN
= V
IH
or V
IL
I
OH
= -3.0mA
I
OH
= -15.0mA
I
OH
= -32.0mA
Output LOW Voltage
Power Down Disable
V
OL
I
OFF
V
OH
V
OL
I
ODL
I
ODH
V
CC
= Min, V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
OUT
≤
4.5V
V
CC
= Min, V
IN
= V
IH
or V
IL
V
CC
= Min, V
IN
= V
IH
or V
IL
I
OH
= -24.0mA
I
OL
= 24mA
I
OL
= 64mA
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max
V
CC
= Max
V
CC
= Max
V
CC
= Max
V
CC
= Max
V
CC
= Max
V
CC
= Min, I
IN
= -18mA
V
CC
= Max (Note 21), V
OUT
= GND
V
CC
= Max (Note 21), V
OUT
= 2.5V
V
CC
= Max, V
OUT
= 4.5V
V
IN
= Vcc
V
IN
= Vcc
V
IN
= GND
V
IN
= GND
V
OUT
= 2.7V
V
OUT
= 0.5V
2.0
-
-
-
-
-
-
-
-
-80
-50
-
-
-
-
-
-
-
-
-
-
-0.7
-140
-
-
100
-
0.8
1
-1
1
-1
1
-1
-1.2
-225
-180
±100
-
V
V
µA
µA
µA
µA
µA
µA
V
mA
mA
µA
mV
CD74FCT16511T OUTPUT DRIVE SPECIFICATIONS
Over the Operating Range, T
A
= -40
o
C to 85
o
C, V
CC
= 5.0V
±10%
Output HIGH Voltage
2.5
2.4
2.0
-
-
3.5
3.5
3.0
0.2
-
-
-
-
0.55
±100
V
V
V
V
µA
CD74FCT162511T OUTPUT DRIVE SPECIFICATIONS
Over the Operating Range, T
A
= -40
o
C to 85
o
C, V
CC
= 5.0V
±10%
Output HIGH Voltage
Output LOW Voltage
Output LOW Current
Output HIGH Current
2.4
-
60
-60
3.3
0.3
115
-115
-
0.55
150
-150
V
V
mA
mA
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V (Note 21)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
OUT
= 1.5V (Note 21)
5
