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CD74HC648EN

IC,BUS TRANSCEIVER,SINGLE,8-BIT,HC-CMOS,DIP,24PIN,PLASTIC

器件类别:逻辑    逻辑   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Renesas(瑞萨电子)
Reach Compliance Code
not_compliant
控制类型
INDEPENDENT CONTROL
计数方向
BIDIRECTIONAL
JESD-30 代码
R-PDIP-T24
JESD-609代码
e0
逻辑集成电路类型
REGISTERED BUS TRANSCEIVER
最大I(ol)
0.006 A
位数
8
功能数量
1
端子数量
24
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
INVERTED
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP24,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
电源
2/6 V
Prop。Delay @ Nom-Sup
60 ns
认证状态
Not Qualified
表面贴装
NO
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
触发器类型
POSITIVE EDGE
文档预览
Semiconductor
January 1998
N
OM
REC
OT
R
D FO
DE
MEN
D
NEW
ESI
GNS
CD74HC646,
CD74HC648
High Speed CMOS Logic
Octal Bus Transceiver/Register, Three-State
Description
The Harris CD74HC646 and CD74HC648 are octal bus
transceivers/registers with three-state non-inverting outputs.
The Harris CD74HC648 is an octal bus transceiver/register
with three-state inverting outputs. These devices are bus
transceivers with D-type flip-flops which act as internal
storage registers. Data on the A bus or the B bus can be
clocked into the registers on the LOW-to-HIGH transition of
either CAB or CBA clock inputs. Outputs enable (OE) and
direction (DIR) inputs control the transceiver functions. Data
present at the high impedance output can be stored in either
register or both but only one of the two buses can be enabled
as outputs at any one time. The select controls (SAB and
SBA) can multiplex stored and transparent (real time) data.
The direction control determines which data bus will receive
data when the output enable (OE) is LOW. In the high
impedance mode (output enable HIGH), A data can be stored
in one register and B data can be stored in the other register.
The clocks are not gated with the direction (DIR) and output
enable (OE) terminals; data at the A or B terminals can be
clocked into the storage flip-flops at any time.
Features
• Independent Registers for A and B Buses
• CD74HC646 Non-Inverting
• CD74HC648 Inverting
• Three-State Outputs
• Drives 15 LSTTL Loads
• Typical Propagation Delay = 12ns (A to B, B to A) at
V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
PKG.
NO.
E24.3
M24.3
M24.3
Pinout
CD74HC646, CD74HC648
(PDIP, SOIC)
TOP VIEW
CD74HC648EN
CD74HC646M
CD74HC648M
NOTES:
CAB 1
SAB 2
DIR 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 V
CC
23 CBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1998
File Number
1664.1
1
CD74HC646, CD74HC648
Functional Diagram
A0
A1
A2
A
DATA
PORT
A3
A4
A5
A6
A7
4
5
6
7
8
9
10
11
21
OE
DIR
FLIP-FLOP
CLOCKS
DATA
SOURCE
SELECTION
INPUTS
CAB CLOCK
CBA CLOCK
SAB SOURCE
SBA SOURCE
3
1
23
2
22
20
19
18
17
16
15
14
13
B0
B1
B2
B3
B4
B5
B6
B7
B
DATA
PORT
GND = PIN 12
V
CC
= PIN 24
FUNCTION TABLE
INPUTS
DATA I/O
(NOTE 3)
A0 THRU
A7
Input
B0 THRU
B7
Not
Specified
Input
OPERATION OR FUNCTION
OE
X
DIR
X
CAB
X
H or L
X
X
X
H or L
CBA
X
H or L
X
H or L
X
X
SAB
X
SBA
X
CD74HC646
Store A, B Unspecified
CD74HC648
Store A, B Unspecified
X
X
X
X
Not
Specified
Input
Store B, A Unspecified
Store B, A Unspecified
H
H
L
L
L
L
NOTE:
X
X
L
L
H
H
X
X
X
X
L
H
X
X
L
H
X
X
Input
Store A and B Data
Isolation, Hold Storage
Store A and B Data
Isolation, Hold Storage
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
Input
Output
Real-Time A Data to B Bus
Stored A Data to B Bus
3. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data inputs functions are always
enabled, i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs. To prevent excess currents in the
High-Z modes all I/O terminals should be terminated with 10kΩ resistors.
2
CD74HC646, CD74HC648
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V.
. . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 4)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Three-State Leakage
Current
I
I
I
CC
I
OZ
V
CC
or
GND
V
CC
or
GND
V
IL
or V
IH
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-
-6
-7.8
0.02
0.02
0.02
-
6
7.8
-
0
V
O
=
V
CC
or
GND
2
4.5
6
-
4.5
6
2
4.5
6
-
4.5
6
6
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
8
±0.5
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
80
±5
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
160
±10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
3
CD74HC646, CD74HC648
Prerequisite for Switching Specifications
25
o
C
PARAMETER
HC TYPES
Maximum Frequency
f
MAX
2
4.5
6
Setup Time Data to Clock
t
SU
2
4.5
6
Hold Time Data to Clock
t
H
2
4.5
6
Clock Pulse Width
t
W
2
4.5
6
6
30
35
60
12
10
35
7
6
80
16
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
25
29
75
15
13
45
9
8
100
20
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
90
18
15
55
11
9
120
24
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
V
CC
(V)
MIN
TYP
MAX
-40
o
C TO 85
o
C
MIN
TYP
MAX
-55
o
C TO 125
o
C
MIN
TYP
MAX
UNITS
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
25
o
C
-40
o
C TO
85
o
C
MAX
MIN
MAX
-55
o
C TO
125
o
C
MIN
MAX
UNITS
PARAMETER
HC TYPES
Propagation Delay
Store A Data to B Bus
Store B Data to B Bus (646)
SYMBOL
TEST
CONDITIONS
V
CC
(V)
MIN
TYP
t
PHL
, t
PLH
C
L
= 50pF
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
-
-
-
20
-
-
-
12
-
220
44
-
37
240
48
-
41
135
27
-
23
-
-
-
-
-
-
-
-
-
-
-
-
275
55
-
47
300
60
-
51
170
34
-
29
-
-
-
-
-
-
-
-
-
-
-
-
330
66
-
56
360
72
-
61
205
41
-
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PHL,
t
PLH
Store A Data to B Bus
Store B Data to B Bus (648)
C
L
= 50pF
A Data to B Bus
B Data to A Bus (646)
t
PLH,
t
PHL
C
L
= 50pF
4
CD74HC646, CD74HC648
Switching Specifications
C
L
= 50pF, Input t
r
, t
f
= 6ns
(Continued)
25
o
C
PARAMETER
A Data to B Bus
B Data to A Bus (648)
SYMBOL
t
PLH
, t
PHL
TEST
CONDITIONS
C
L
= 50pF
V
CC
(V)
2
4.5
C
L
= 15pF
C
L
= 50pF
Select to Data (646)
t
PLH
, t
PHL
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
Select to Data (648)
t
PLH
, t
PHL
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
Three-State Disabling Time
Bus to Output or Register to
Output
t
PLZ
, t
PHZ
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
Three-State Enabling Time
Bus to Output or Register to
Output
t
PZL
, t
PZH
C
L
= 50pF
5
6
2
4.5
C
L
= 15pF
C
L
= 50pF
Output Transition Time
t
TLH
, t
THL
C
L
= 50pF
5
6
2
4.5
C
L
= 50pF
Input Capacitance
Three-State Output
Capacitance
Maximum Frequency
Power Dissipation Capacitance
(Notes 5, 6)
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per package.
6. P
D
= V
CC2
C
PD
f
i
Σ
V
CC2
C
L
f
o
where f
i
= Input Frequency, f
o
= Output Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
C
IN
C
O
C
L
= 50pF
-
6
-
-
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
TYP
-
-
12
-
-
-
14
-
-
-
16
-
-
-
14
-
-
-
14
-
-
-
-
-
-
MAX
150
30
-
26
170
34
-
29
190
38
-
32
175
35
-
30
175
35
-
30
60
12
10
10
20
-40
o
C TO
85
o
C
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
190
38
-
33
215
43
-
37
240
48
-
39
220
44
-
37
220
44
-
37
75
15
13
10
20
-55
o
C TO
125
o
C
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
225
45
-
38
255
51
-
43
285
57
-
48
265
53
-
45
265
53
-
45
90
18
15
10
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
f
MAX
C
PD
C
L
= 15pF
-
5
5
-
-
60
52
-
-
-
-
-
-
-
-
-
-
MHz
pF
5
查看更多>
参数对比
与CD74HC648EN相近的元器件有:CD74HC648M。描述及对比如下:
型号 CD74HC648EN CD74HC648M
描述 IC,BUS TRANSCEIVER,SINGLE,8-BIT,HC-CMOS,DIP,24PIN,PLASTIC IC,BUS TRANSCEIVER,SINGLE,8-BIT,HC-CMOS,SOP,24PIN,PLASTIC
是否Rohs认证 不符合 不符合
厂商名称 Renesas(瑞萨电子) Renesas(瑞萨电子)
Reach Compliance Code not_compliant not_compliant
控制类型 INDEPENDENT CONTROL INDEPENDENT CONTROL
计数方向 BIDIRECTIONAL BIDIRECTIONAL
JESD-30 代码 R-PDIP-T24 R-PDSO-G24
JESD-609代码 e0 e0
逻辑集成电路类型 REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
最大I(ol) 0.006 A 0.006 A
位数 8 8
功能数量 1 1
端子数量 24 24
最高工作温度 85 °C 125 °C
最低工作温度 -40 °C -55 °C
输出特性 3-STATE 3-STATE
输出极性 INVERTED INVERTED
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 DIP SOP
封装等效代码 DIP24,.3 SOP24,.4
封装形状 RECTANGULAR RECTANGULAR
封装形式 IN-LINE SMALL OUTLINE
电源 2/6 V 2/6 V
Prop。Delay @ Nom-Sup 60 ns 72 ns
认证状态 Not Qualified Not Qualified
表面贴装 NO YES
技术 CMOS CMOS
温度等级 INDUSTRIAL MILITARY
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 THROUGH-HOLE GULL WING
端子节距 2.54 mm 1.27 mm
端子位置 DUAL DUAL
触发器类型 POSITIVE EDGE POSITIVE EDGE
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