power amplifier GaAs MMIC intended for use in portable tele-
phone handsets and data communications products for wireless
communications. It meets the handset requirements for cellular
AMPS, and the CDMA and TDMA digital standards for the US
cellular wireless communications. CMM0530-LC is a member
of the new
Triniti DX Pro
™
amplifier family whose members
are pin-compatible and all operate under 3.5V bias voltage. The
CMM0530-LC is packaged in a low-cost, plastic, LCC-8 power
package. It has low thermal impedance and low RF loss. The
device requires minimum amount of external biasing and RF
matching circuits.
Absolute Maximum Ratings
Parameter
Rating
Parameter
Rating
Parameter
Rating
Drain Voltage (+Vd)
Drain Current (Id)
RF Input Power
DC Gate Voltage (-Vg)
+5.5 V*
1.8 A
+10 dBm*
-3.0 V*
Power Dissipation
Thermal Resistance
Storage Temperature
5W
20°C/W
-65°C to +150°C
Operating Temperature
Channel Temperature
Soldering Temperature
-40°C to +90°C
150°C
260°C for 5 Sec.
* Max (+Vd) and (-Vg) under linear operation. Max potential difference across the device at 1 dB gain compression point (2Vd + |-Vg|) not to exceed the minimum breakdown voltage (Vbr) of +12V.
Recommended Operating Conditions
Parameter
Typ
Units
Parameter
Typ
Units
Drain Voltage (+Vd)
3.0 to 4.2
Volts
Operating Temperature (PC Board)
-30 to +80
°C
Application Information
The CMM0530-LC is a two-stage amplifier that requires
both positive and negative power supplies for proper operation.
It is essential that the negative supply be applied first during
turn-on and last during turn-off. Otherwise, the device may be
damaged.
The CMM0530-LC can be operated over a wide range of
positive and negative voltages to obtain various power, linearity
and efficiency performance. However, it is important to keep
the maximum DC power and the bias voltages within the speci-
fied absolute maximum rating to prevent over stressing the
device either electrically or thermally.
Design Considerations
Biasing
Negative gate voltages are necessary to set the bias
currents of the two FET stages in the CMM0530-LC. The first
stage gate bias voltage is applied to Vg1 (Pin 2). The second
stage gate bias voltage is applied to Vg2 (Pin 1). It is desirable
to use one or more DACs (digital to analog converters) along
3236 Scott Boulevard
Santa Clara, California 95054
with appropriate resistor divider networks, when necessary, in
order to adjust the quiescent currents to within 10 mA of the
targeted values. As an example, for CDMA applications the tar-
get quiescent current of the second FET is 120 mA, while that
of the first is 50 mA. The total quiescent is 170 mA. It is also
recommend that the quiescent currents be set in the following
sequence: the second stage FET is set first, followed by the first
stage FET. The negative supply voltages control the quiescent
currents through each FET and, therefore, control the output
power, adjacent channel power ratio, and the currents at full
output power.
The positive supply voltages are applied to Pins 5, 6 and 7.
It is very important to provide adequate de-coupling
between the RF and the DC signals in designing the DC bias
circuit. Inadequate by-pass capacitance around the DC supply
lines and inductance can compromise the adjacent channel
power ratio (ACPR), or reduce power gain and/or create oscil-
lations. The recommend DC by-pass capacitance and low-pass
– Continued on Page 2 –
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Fax: (408) 986-5095
CMM0530-LC
Electrical Characteristics
Advanced Product Information - May 1999
(2 of 4)
Unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+Vd) = 3.5 V, in Celeritek test fixture.
Digital Bias
Parameter
Condition
Min
Typ
Max
Analog Bias
Min
Typ
Max
Units
Frequency Range
Pout - TDMA Operation
Pout - CDMA Operation
Pout - Analog Operation
Efficiency
824
+30.0
+28.5
928
824
928
Meets IS-136 TDMA mask
Meets IS-98 CDMA mask
AMPS (under dual mode operation)
IS-136 TDMA @ +30 dBm
IS-95 CDMA @ +28 dBm
AMPS @ +31.5 dBm
(under dual mode operation)
Harmonics
2nd @ Pout = +31.5 dBm
3rd @ Pout = +31.5 dBm
Adjacent Channel Power
Pout = +30 dBm TDMA ±30 KHz
Alternate Channel Power
Pout = +30 dBm TDMA ±60 KHz
Adjacent Channel Power
Pout = +28 dBm CDMA ±898 KHz
Alternate Channel Power
Pout = +28 dBm CDMA ±1980 KHz
Noise Power in Receive Band 30 kHz BW
Gain
@ Pout = +28.5 dBm, +30 dBm
@ Pout = +31.5 dBm
Gain Ripple
824-849 or 880-910 MHz
Gain Variation
Over supply voltage
Gain Variation
Over temperature
Power Output Control Range Vdd = 0 to 3.5 V
Quiescent Current
No RF, TDMA mode
No RF, CDMA mode
Noise Figure
VSWR
Input (In Celeritek test fixture)
Stability
8:1 VSWR in band
10:1 VSWR out of band
– Continued from Page 1 –
+31.5
42
37
55
57
-30
-35
MHz
dBm
dBm
dBm
%
%
%
dBc
dBc
dBc
dBc
dBc/30 KHz
dBc/30 KHz
dBm
dB
dB
dB
dB/V
dB/°C
dB
mA
mA
dB
dBc/30 KHz
dBc/30 KHz
-26
-45
-45
-55
26
-94
29
24
1.5
2
0.03
50
200
170
3.5
2.0:1
-80
-80
2
0.03
27
1.5
3.5
2.0:1
-80
-80
in-line inductance are shown in the evaluation board on page 4.
Matching Circuits
Output matching and input matching cir-
cuits are required to achieve the RF specifications in this data
sheet. The recommend matching circuits are identical to the
matching circuits for the evaluation board shown on Page 4.
For output power matching, shunt capacitors along the trans-
mission line connected to Pins 6 and 7 as well as the bond
wire inside the package from the output leads to the output
FET are used to transform 50Ω impedance to the load line
resistance of the output FET. The placements and the values
of the capacitor are important in achieving the performance
desired. Matching circuits for frequencies other than the one
shown can be achieved by changing the capacitor value and
the placement position of the capacitor. The device can be
designed to work from UHF to around 3 GHz.
Supply Ramping
To obtain power ramping, gate supply con-
trol is recommended. Drain supply voltage can also be used.
Modulation
When biased as specified, the CMM0530-LC will
achieve the required adjacent channel response for the digital
system specified. Celeritek tests each product under digital
modulation to ensure correlation to customer applications.
Thermal
1. The copper pad on the backside of the CMM0530-LC must
be soldered to the ground plane.
2. All 8 leads of the package must be soldered to the appropri-
ate electrical connection.
Typical Performance
Gain & IS-136 TDMA Output Power
vs Frequency Over Voltage @ +25°C
Power Out, dBm
31.5
3.3 V
3.0 V
29.5
2.7 V
3.3 V
3.0 V
2.7 V
27.5
824
Frequency, MHz
849
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
Gain, dB
29.5
CMM0530-LC
Advanced Product Information - May 1999
Typical Performance
IS-136 TDMA Spectral Mask (Vdd = 3.5V)
IS-98 CDMA Spectral Mask (Vdd = 3.5V)
(3 of 4)
Id & IS-136 TDMA Channel Power vs
Power Output (3.5V, 836.5 MHz)
1000
700
Id & IS-98 CDMA Channel Power vs
Power Output (3.5V, 836.5 MHz)
Channel Power, dBc/30 kHz
Efficiency, %
Id, mA
Id, mA
600
400
100
-45
-60
-75
22.15
24.25
26.4
28.5
Power Output, dBm (1.25 MHz BW)
Adjacent channel power (worst case ±0.898 MHz)
Adjacent channel power (worst case ±1.98 MHz)
200
-20
-40
-60
8
13.75
19.5
25.25
31
Power Output, dBm (30 kHz BW)
Adjacent channel power (worst case, Fc ±30 kHz)
Alternate channel power (worst case, Fc ±60 kHz)
Channel Power, dBc
20
TDMA Power Output and Efficiency vs Input Power
(3.5V, 836.5 MHz)
Power Output, dBm
Power Output, dBm
35
25
15
5
75
50
25
0
+1
35
25
15
5
CDMA Power Output and Efficiency
vs Input Power (3.5V, 836.5 MHz)
Efficiency, %
50
25
0
-0.5
-24
-17
-11
-5
Input Output, dBm
-9.0
-6.9
-4.9
-2.8
Input Output, dBm
Wideband Gain & Return Loss
vs Frequency @ 3.5V, +25°C
40
Gain, dB
30
20
10
0
Input Return Loss
Gain
-20
Output Return Loss
.3
.6
1.2
1.8
Frequency, GHz
2.4
3.0
-30
-40
3236 Scott Boulevard
Santa Clara, California 95054
Return Loss, dB
0
-10
Phone: (408) 986-5060
Fax: (408) 986-5095
CMM0530-LC
Recommended Matching Topology
Advanced Product Information - May 1999
(4 of 4)
Note: This schematic represents the topology of the matching circuit recommended by Celeritek.
Vgg
130
1.5 K
C3
100 pF
8
7
6
5
C8
5600
pF
C10
5600
pF
38
Ω
6°@
835 MHz
C5
2.2 pF
L3
47 nH
C6
10 pF
C11
100 pF
C7
100 pF
N/C
45
Ω
4°@
835 MHz
Evaluation Board Schematic
Board substrate:
ER = 4.60
Thickness = 0.031 in.
50
Ω
RF OUT
C2
.01 µF
1
RF IN
C1
10 µF
C4
100 pF
2
3
65
Ω
8°
835
MHz
N/C
4
50
Ω
L1
3.3 nH
CMM0530-LC
L2
47 nH
C9
.01
µF
C13
100
µF
C12
.01 µF
Vdd
R3
51 K
Physical Dimensions
Ordering Information
The CMM0530-LC is available in a surface mount wide-body MSOP-8 power package and devices are available in tape and reel.
Part Number for Ordering
Package
CMM0530-LC-00S0
LCC-8 CDMA surface mount power package
CMM0530-LC-00T0
LCC-8 TDMA surface mount power package
CMM0530-LC-00ST
LCC-8 CDMA surface mount power package in tape and reel
CMM0530-LC-00TT
LCC-8 TDMA surface mount power package in tape and reel
PB-CMM0530-LC-00S0
Evaluation Board with SMA connectors for CMM0530-LC-00S0
PB-CMM0530-LC-00T0
Evaluation Board with SMA connectors for CMM0530-LC-00T0
Celeritek reserves the right to make changes without further notice to any products herein. Celeritek makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Celeritek assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Celeritek does not convey any license under its patent
rights nor the rights of others. Celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Celeritek product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Celeritek products for any such unintended or unauthorized application, Buyer shall indemnify and hold Celeritek and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Celeritek was negligent
regarding the design or manufacture of the part. Celeritek is a registered trademark of Celeritek, Inc. Celeritek, Inc. is an Equal Opportunity/Affirmative Action Employer.
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