CoreSDLC
Product Summary
Intended Use
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ISDN D-Channel
X.25 Networks
Frame Relay Networks
Custom Serial Interfaces
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Netlist Version
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Structural Verilog and VHDL Netlists (with and
without I/O pads) Compatible with Actel's
Designer Software Place-and-Route Tool
Compiled RTL Simulation
Supported in Actel Libero IDE
Model
Fully
RTL Version
Verilog and VHDL Core Source Code
Core Synthesis Scripts
Key Features
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Based on Intel's 80C152 Global Serial Channel
Working in SDLC Mode
Single and Double-Byte Address Recognition
Address Filtering Enables Multicast and Broadcast
Addresses
16-bit (CRC-16) and 32-bit (CRC-32) Frame Check
Sequence
NRZ and NRZI Data Encoding
Automatic Bit Stuffing/Stripping
3-Byte Deep Internal Receive and Transmit FIFOs
Full or Half-Duplex Operation
Variable Baud Rate
External or Internal Transmit and Receive Clocks
Optional Preamble Generation
Programmable Interframe Space
Raw Transmit and Receive Testing Modes
All Major Actel Device Families Supported
Testbench (Verilog and VHDL)
Synthesis and Simulation Support
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Synthesis: Synplicity
®
, Synopsys
®
(Design Compiler
®
/ FPGA Compiler
TM
/ FPGA Express
TM
), Exemplar
TM
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Core Verification
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Comprehensive VHDL and Verilog Testbenches
User can Modify Testbench Using Existing Format
to Add Custom Tests
Contents
General Description ................................................... 1
CoreSDLC Device Requirements ................................ 3
CoreSDLC Verification ................................................ 3
I/O Signal Descriptions ............................................... 3
SDLC Protocol Overview ............................................ 4
Data Encoding ............................................................ 7
Bit Stuffing ................................................................. 7
Special Function Registers ......................................... 8
Modes of Operation ................................................ 15
General Description of the Transmitter .................. 16
General Description of the Receiver ....................... 17
Ordering Information .............................................. 20
List of Changes ......................................................... 21
Datasheet Categories ............................................... 21
Supported Families
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Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
SX-A
RTSX-S
Core Deliverables
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Evaluation Version
–
Compiled RTL Simulation Model Fully
Supported in Actel Libero
®
Integrated Design
Environment (IDE)
December 2005
© 2005 Actel Corporation
v 4 .0
1
CoreSDLC
General Description
The CoreSDLC macro provides a high-speed synchronous
serial communication controller that utilizes the
synchronous data link control (SDLC) protocol. Operation
of the controller is similar to that used in the Intel
8XC152 Global Serial Channel (GSC) device working in
SDLC mode under CPU control. Communication with a
CPU is realized through the Special Function Register
(SFR) interface and three interrupt sources. This enables
interfacing CoreSDLC easily with any CPU.
CoreSDLC consists of three primary blocks, as shown in
Figure 1:
1. Receive logic – decodes and bit strips incoming
data stream, detects flags, checks CRC, and shifts
data into an internal three-byte deep receive FIFO.
The receive logic also performs address detection,
clock recovery, and frame sequencing.
2. Transmit logic – shifts data out of an internal
three-byte deep transmit FIFO, generates a CRC,
performs bit stuffing, flag insertion, and encoding
of the transmit data stream. The transmit logic
also performs frame sequencing.
3. SFR logic – provides a simple interface to an
external processor or controller.
sfrdatai[7:0]
sfrdatao[7:0]
sfraddr[6:0]
sfrw
sfrr
SFR
tv
re
rv
ptv
pre
Shift Register
CRC
Checker
Flag
Detection
Receive
Bit
Stripping
Data
Decoder
rxd
FIFO
Data
Address
Detection
Receive Frame
Sequencer
Clock
Recovery
rxc
Internal Signals
Data
FIFO
Transmit Frame
Sequencer
Transmit
txc
den
Shift Register
CRC
Generator
Bit
Stuffing
Flag
Insertion
Data
Encoder
txd
prv
Figure 1 •
CoreSDLC Block Diagram
CoreSDLC Device Requirements
CoreSDLC has been implemented in several of Actel's device families. A summary of the implementation data is listed in
Table 1.
Table 1 •
CoreSDLC Device Utilization and Performance
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
Sequential
408
408
384
400
Combinatorial
878
878
1337
537
Total
1286
1286
1721
577
Utilization
Device
AFS600
A3PE600-2
APA150-STD
AX125-3
Total
10%
10%
28%
47%
Performance
100 MHz
100 MHz
65 MHz
140 MHz
Note:
Data in this table were achieved using typical synthesis and layout settings.
2
v4.0
CoreSDLC
Table 1 •
CoreSDLC Device Utilization and Performance (Continued)
Cells or Tiles
Family
SX-A
RTSX-S
Sequential
403
391
Combinatorial
580
545
Total
983
936
Utilization
Device
A54SX32A-3
RT54SX32S-2
Total
35%
33%
Performance
120 MHz
75 MHz
Note:
Data in this table were achieved using typical synthesis and layout settings.
CoreSDLC Verification
The comprehensive verification simulation testbench
(included with the Netlist and RTL versions of the core)
verifies correct operation of the CoreSDLC macro with
respect to the SDLC protocol.
The verification testbench applies over 90 tests to the
CoreSDLC macro, including:
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Receive valid in normal mode tests
Receive valid in raw mode tests
Receive with errors tests
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Receive clock recovery tests
Transmit tests
Using the supplied user testbench as a guide, the user
can easily customize the verification of the core by
adding or removing tests.
I/O Signal Descriptions
The port signals for the CoreSDLC macro are defined in
Table 2
and illustrated in
Figure 2 on page 4.
All signals
are either “Input” (input-only) or “Output” (output-
only).
Table 2 •
CoreSDLC I/O Signal Descriptions
Name
nreset
clk
sfrdatai[7:0]
sfrdatao[7:0]
sfraddr[6:0]
sfrwe
sfrra
rv
re
tv
prv
pre
ptv
rxd
txd
rxc
txc
den
rdn
Type
Input
Input
Input
Output
Input
Input
Input
Output
Output
Output
Output
Output
Output
Input
Output
Input
Input
Output
Output
Description
Active-low asynchronous reset
System Clock: reference clock for all internal logic
SFR data bus input
SFR data bus output
SFR address bus
SFR write enable
SFR read acknowledge
Receive valid interrupt
Receive error interrupt
Transmit valid interrupt
Receive valid interrupt priority
Receive error interrupt priority
Transmit valid interrupt priority
Receive input
Transmit output
Receive clock
Transmit clock
Active-low external driver enable
Receive done interrupt
Note:
All signals are active-high unless otherwise indicated.
v4.0
3
CoreSDLC
SDLC Protocol Overview
sfrdatao[7:0]
sfrdatai[7:0]
nreset
clk
rxc
rxd
txc
txd
den
rdn
sfraddr[6:0]
sfrwe
sfrra
CoreSDLC
ptv
pre
prv
tv
re
rv
The SDLC protocol has two types of network nodes:
primary and secondary. There is always one primary node
in the network, but there may be one or more secondary
nodes. The primary node controls operation of the
secondary nodes and manages the network. Secondary
nodes can send information only if the primary node has
given them permission. This is accomplished by the
primary node polling the secondary nodes in a
predetermined order to see if they need to send
information.
As shown in
Figure 3 on page 4,
SDLC nodes are
connected in one of the three following configurations:
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Point-to-point, when there is one primary and
only one secondary node
Multi-drop, when there is one primary and
multiple secondary nodes
Ring, when all nodes are connected in a loop and
the output channel of one node is connected to
the input channel of the next node.
Figure 2 •
CoreSDLC I/O Signal Diagram
a) Point-to-Point Network
Primary
Secondary
b) Multi-Drop Network
Primary
Secondary
Secondary
Secondary
c) Ring Network
Primary
Secondary
Secondary
Secondary
Figure 3 •
SDLC Network Configurations
4
v4.0
CoreSDLC
SDLC Frames
The SDLC frame consists of six fields.
Table 3
shows the order of the fields in the SDLC frame.
Table 3 •
SDLC Frame
BOF
ADDRESS
CONTROL
INFO
CRC
EOF
BOF (Begin of Frame)
The BOF flag, which indicates the beginning of a frame,
is defined as the value 01111110. The controller's
hardware properly distinguishes normal data from the
BOF flag because of a process called
bit stuffing,
which is
described in
"Bit Stuffing" on page 7.
Bit stuffing,
performed by the transmit logic, is the process of
inserting a '0' after each five consecutive '1' values. The
receiver logic utilizes a process called
bit stripping.
Each
time a sequence of five '1' values followed by a '0' is
received, the controller automatically removes this '0'
from the incoming bitstream. BOF is one of two possible
bit combinations that consist of more than five
consecutive '1' values. The BOF marks the beginning of a
frame and also assures receive clock synchronization.
however, the hardware address checking only works up
to 16-bit addresses. There is also one special address
defined in SDLC called "broadcast address," consisting of
all '1' values. All stations connected to the network
receive the frame containing the broadcast address.
CoreSDLC transmits the address field’s least significant
bit (LSB) first.
CONTROL
This field is used for initializing the system and managing
tasks, such as data acknowledge, identifying frame
sequence numbers, and indicating the end of the
message. CoreSDLC does not provide any functions for
managing the CONTROL field, so the user’s software is
responsible for insertion and interpretation.
There are three types of control fields, depending on the
type of SDLC frame used:
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Information frame (Table
4)
Supervisory frame (Table
5)
Nonsequenced (or unnumbered) frame (Table
6)
ADDRESS
In standard SDLC, an eight-bit field in the frame is used
to identify the target controller for which the frame is
intended. In CoreSDLC, this field may also be 16 bits in
length, extending the addressing capability. The address
length can be further extended by the user’s software;
Table 4 •
Control Field – Information Format
Bit Position
Function
7
6
Reception Sequence
5
4
Poll /Final
3
2
Sending Sequence
1
0
1
Table 5 •
Control Field – Supervisory Format
Bit Position
Function
7
6
Reception Sequence
5
4
Poll / Final
3
Mode
2
1
0
0
1
Table 6 •
Control Field – Nonsequenced Format
Bit Position
Function
7
6
Command / Response
5
4
Poll / Final
3
2
1
0
0
1
Command / Response
The CONTROL field of the information frame contains a
three-bit sending sequence number (the number of the
current frame) and a three-bit reception sequence
number (the expected number of the next frame). The
same reception sequence number is also part of the
control field in the supervisory frame. In both cases, it is
used for frame acknowledgement. If the receiving
station has no data to send, it acknowledges the received
frames by sending a supervisory frame in response.
However, if the receiving station wants to send data, the
response may be part of the information frame
(piggybacking). This allows for full-duplex operation in
which two continuous data streams are transmitted in
both directions without supervisory frame insertion.
Up to seven information frames can be sent without
acknowledgement. Due to this capability, continuous
transmission (continuous ARQ) is possible, which means
that the CoreSDLC transmitter does not need to wait for
an acknowledgement.
The poll/final bit in each control field is used for polling
secondary nodes by a primary node (poll) and for
indicating the end of the message (final).
v4.0
5
