CPLL-018-200.00,CPLL-018-200.00 pdf中文资料,CPLL-018-200.00引脚图,CPLL-018-200.00电路-Datasheet-电子工程世界

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CPLL-018 Model

5X7 mm SMD,

3.3V, CMOS

Frequency Range:

Frequency Stability:

Temperature Range:

Operating:

(Option M)

(Option X)

Storage:

Input Voltage:

Input Current:

Output:

Symmetry:

Rise/Fall Time:

Logic:

Load:

Jitter:

Aging:

ree

dF S

Le oH ant

R pli

1.544MHz to 200MHz

±25ppm, ±50ppm, ±100ppm

Programmable

Clock Oscillator

PLL Based Design

0°C to 70°C

-20°C to 70°C

-40°C to 85°C

Designed to meet today's

-55°C to 120°C

requirements for economical

3.3V ± 0.3V

3.3V applications. Available

45mA Max

on 16mm tape and reel in

CMOS

quantities of 1K.

40/60% Max @ 50% Vdd

10ns Max @ 20/% to 80% Vdd

"0" = 80% Vdd Max

"1" = 90% Vdd Min

15pF

150pS pk-pk Max

<3ppm 1st/yr, <1ppm every year hereafter

SUGGESTED PAD LAYOUT

0.055 Typ

(1.40 Typ)

0.045 ±0.008

(1.14 ±0.20)

0.165

(4.19)

0.071 SQ

(1.80)

Dimensions inches (mm)

All dimensions are Max unless otherwise specified.

0.295 Max

(7.50)

P/N

Freq DC

Denotes pad 1

0.204 Max

(5.02)

0.075 Max

(1.80)

0.200 ±0.005

(5.08 ±0.13)

0.200

(5.08)

0.01uF Bypass Capacitor Recommended

RECOMMENDED REFLOW SOLDERING PROFILE

TEMPERATURE

260°C

217°C

200°C

150°C

Ramp-Up

3°C/Sec Max.

Critical Temperature

Zone

Ramp-Down

6°C/Sec.

Crystek Part Number Guide

CPLL-018 X- 25 - 200.000

#1 Crystek Clock PLL Osc.

#2 Model

#3 Temp. Range: Blank= 0/70°C, M= -20/70°C, X= -40/85°C

#4 Stability: (see Table 1)

#5 Frequency in MHz: 3 or 6 decimal places

Stability Indicator

Blank (std)

± 100ppm

± 25ppm

± 50ppm

Preheat

180 Secs. Max.

8 Minutes Max.

90 Secs. Max.

Example:

CPLL-018X-25-200.000 = 3.3V Tristate, -40/85°C, 25ppm, 200.000 MHz

CPLL-018-50-19.660800 = 3.3V Tristate, 0/70, 50ppm, 19.660800 MHz

Table 1

260°C for

10 Secs. Max.

NOTE: Reflow Profile with 240°C peak also acceptable.

OUT

pin 4

Vdd

OUT

Tri-State Function

Function pin 1

Open

"1" level 2.4V Min

"0" level 0.4V Max

Output pin

Active

High Z

pin 3

OSC.

GND

PWR

Supply

O/P Load

incl Probe Cl

Bypass

Cap.

pin 1

pin 2

High Impedance

GND or "LOW"

Oscillation

OPEN or "HIGH"

Specifications subject to change without notice.

TD-040405 Rev.C

参数对比

与CPLL-018-200.00相近的元器件有：CPLL-018-25-200.00、CPLL-018X-25-200.00、CPLL-018、CPLL-018M-25-200.00、CPLL-018X-50-200.00、CPLL-018M-50-200.00、CPLL-018X-200.00、CPLL-018-50-200.00、CPLL-018M-200.00。描述及对比如下：

型号	CPLL-018-200.00	CPLL-018-25-200.00	CPLL-018X-25-200.00	CPLL-018	CPLL-018M-25-200.00	CPLL-018X-50-200.00	CPLL-018M-50-200.00	CPLL-018X-200.00	CPLL-018-50-200.00	CPLL-018M-200.00
描述	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS