CY22388, CY22389, CY22391
Factory Programmable Quad PLL Clock
Generator with VCXO
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
16-/20-pin TSSOP and 32-pin QFN packages
3.3V operation with 2.5V output buffer option
Fully integrated phase-locked loops (PLLs)
QFN package
40% smaller than 20-pin TSSOP
22% smaller than 16-pin TSSOP
Selectable Output Frequency
Programmable Output Frequencies
Output Frequency Range of 5–166 MHz
Input Frequency Range
Crystal: 10–30 MHz
External Reference: 1–100 MHz
Analog VCXO
Benefits
■
■
■
■
■
■
Meets most Digital Set Top Box, DVD Recorder, and DTV appli-
cation requirements
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Integration eliminates the need for external loop filter compo-
nents
Meets critical timing requirements in complex system designs
Enables application compatibility
Complete VCXO solution with ±120 ppm (typical pull range)
Logic Block Diagram
FS0
FS1
FS2
Select
Logic
CLKA
PLL1
CLKB
CLKC
XIN
VCXO
XOUT
VIN
PLL2
Dividers
&
Multiplexers
PLL3
CLKF
(CY22389 &
CY22391 only)
(CY22389 &
CY22391 only)
(CY22389 &
CY22391 only)
CLKD
CLKE
PLL4
CLKG
CLKH
OE/PD#
(CY22389 &
CY22391 only)
Pinouts
Figure 1. Pin Diagram - 16-Pin TSSOP CY22388
16-Pin TSSOP
XIN
FS0
FS1
VIN
VDD
VSS
CLKA
CLKB
1
2
3
4
5
6
7
8
CY22388
16
15
14
13
12
11
10
9
XOUT
VDD
FS2
VDD
VSS
CLKE
CLKD
CLKC
Cypress Semiconductor Corporation
Document #: 38-07734 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 13, 2009
[+] Feedback
CY22388, CY22389, CY22391
Figure 2. Pin Diagram - 20-Pin TSSOP CY22389
20- Pin TSSOP
Figure 3. Pin Diagram - 32-Pin TSSOP CY22391
32-Pin QFN
27
XOUT
26
VDD
25
VDD
24
OE/PD#
23
22
FS2
VDD
VDD
VSS
VSS
CLKG
CLKF
21
20
19
18
17
11
16
10
12
13
14
15
9
VDD
32
FS1
31
FS0
NC
29
30
XIN
NC
28
XIN
FS0
FS1
CLKH
VDD
VSS
CLKD
CLKB
CLKA
CLKC
1
2
3
4
5
20
19
18
17
XOUT
VDD
OE/PD#
FS2
VIN
VDD
VSS
CLKG
CLKF
CLKE
VIN
VDD
VDD
VSS
VSS
VSS
1
2
3
4
5
6
7
8
16
CY22389
15
6
7
8
9
10
14
13
12
11
CY22391
VSS
CLKH
CLKC
CLKD
CLKB
CLKA
Pin Definitions
Pin Name
XIN
XOUT
CLKA
CLKB
CLKC
CLKD
CLKE
CLKF
CLKG
CLKH
FS0
FS1
FS2
OE/PD#
VIN
VDD
VSS
NC
Pin Number
16-Pin TSSOP 20-Pin TSSOP
1
16
7
8
9
10
11
n/a
n/a
n/a
2
3
14
n/a
4
5,13,15
6,12
n/a
1
20
9
8
10
7
11
12
13
4
2
3
17
18
16
5,15,19
6,14
n/a
32-Pin QFN
30
27
11
10
14
9
15
17
18
8
31
32
23
24
1
2,3,16,21,22,25,26
4,5,6,7,19,20
12,13,28,29
Pin Description
Crystal Input or Reference Clock Input
Crystal Output (No connect if external clock is used)
Clock Output
Clock Output
Clock Output
Clock Output
Clock Output
Clock Output
Clock Output
Clock Output
Frequency Select 0
Frequency Select 1
Frequency Select 2
Programmable control pin: Output Enable
(active-high) or Power Down (active-low)
Analog Control Input for VCXO
Voltage Supply
Ground
No Connect.
Document #: 38-07734 Rev. *C
CLKE
NC
NC
Page 2 of 10
[+] Feedback
CY22388, CY22389, CY22391
General Description
The CY22388 family of devices has an Analog VCXO (Voltage
Controlled Crystal Oscillator), 4 PLLs, up to 8 clock outputs and
frequency selection capabilities. The frequency selects do not
modify any PLL frequency. Instead they allow the user to choose
between up to 8 different output divider selections depending on
the clock and package configuration. This is illustrated in the
following Frequency Selection tables and Functional Block
Diagram.
There is one programmable OE/PD#. The OE/PD# pin can be
programmed as either an output enable pin or a power down pin.
The OE function can be programmed to disable a selected set of
outputs when low, leaving the remaining outputs running.
Full-chip power down disable all outputs and the PLLs and most
of the active circuitry when low.
In order to minimize PPM (Parts Per Million) error on the clock
outputs, a user must choose a crystal reference frequency that
is a common multiple of the desired PLL frequencies. While this
would be the ideal situation, this is not always the case and the
PLLs have high-resolution counters internally to help minimize
frequency deviation from the desired frequency.
PLL VCO frequencies are generated by the following equation:
F
VCO
= F
REF
* (P / Q)
Where F
REF
is the reference input frequency, P is the PLL
feedback divider and Q is the reference input divider.
A PLL is a feedback system where the VCO frequency divided
by P and reference frequency divided by Q are constantly being
compared and the VCO frequency is adjusted to achieve a
locked state.
Figure 3
is a simplified drawing of a PLL.
Figure 3. PLL system
F
R E F
Factory-Programmable CY22388/89/91
Factory programming is available for high- or low-volume
manufacturing by Cypress. All requests must be submitted to the
local Cypress Field Application Engineer (FAE) or sales repre-
sentative. Once the request has been processed, you will
receive a new part number, samples, and data sheet with the
programmed values. This part number is used for additional
sample requests and production orders.
/Q
V C O
a nd
F
V C O
O th e r
c o m p o n e n ts
/P
Frequency Select Pin Operation
Table 1. CY22388 16-pin TSSOP
Output Signal
CLK A
CLK B
CLK C & CLK D
CLK E
Table 2. CY22389 20-pin TSSOP
Output Signal
CLK A
CLK B & CLK C
CLK D, CLK E, & CLK F
CLK G
CLK H
Table 3. CY22391 32-pin QFN
Output Signal
CLK A
CLK B & CLK C
CLK D, CLK E, & CLK F
CLK G
CLK H
Frequency Selection
Lines
FS2, FS1, FS0
FS1, FS0
FS0
FIXED
COPY OF CLK D
Frequency Selection
Lines
FS2, FS1, FS0
FS1, FS0
FS0
FIXED
COPY OF CLK D
Frequency Selection
Lines
FS2, FS1, FS0
FS1, FS0
S0
FIXED
PLLs
The advantage of having four PLLs is that a single device can
generate up to four independent frequencies from a single
crystal. Generally a design may require up to four oscillators to
accomplish what could be done with a single CY22388.
Each PLL is independent and can be configured to generate a
VCO (Voltage Controlled Oscillator) frequency between
62.5 MHz and 250 MHz. Each PLL can then in turn be divided
down with post dividers to generate the clock output frequency
of the user’s choice. The output divider allows each clock output
to be divided by 1, 2, 3, 4, 5, 6, 8, 9, 10, 12 or 15. The PLL
maximum is reduced to 166 MHz in divide by 1 mode due to
output buffer limitations.
Outputs that allow frequency switching perform the transition
free of glitches. A glitch is defined as a high or low time shorter
than half the smaller of the two periods being switched between.
Extended low time (even many cycles in duration) is acceptable.
Selected clock outputs are capable of being powered off a
separate 2.5V supply. This allows for driving lower voltage swing
inputs. The CY22388/89/91 device still requires 3.3V to power
the oscillator and all other internal PLL circuitry. For the 2.5V
output option please refer to the CY22388 Application Note.
Selected clocks and pinout diagrams are explained in this appli-
cation note.
Clock D can obtain its output from either the reference source or
PLL1/N1 with N1 being defined as the output divider for PLL1.
Clock H is defined as a copy of clock D. Clock D is only available
from PLL1/N1 on the 16-pin package.
For CY22388, CLKB and CLKC have related frequencies. For
CY22389 and CY22391, CLKD and CLKF have related
frequencies, CLKA and CLKB have related frequencies, and
CLKC and CLKE have related frequencies. Related frequencies
come from the same PLL but can have different divider values.
Document #: 38-07734 Rev. *C
Page 3 of 10
[+] Feedback
CY22388, CY22389, CY22391
Analog VCXO
There are three programmable reference operating modes for
the CY22388, CY22389, CY22391 family of devices. The first
mode utilizes an external pullable crystal and incorporates an
internal Analog VCXO.
The second mode configures the internal crystal oscillator to
accept an external driven reference source from 1 to 100 MHz.
The input capacitance on the XIN PIN when driven in this mode
is 15 pF.
The third mode disables the VCXO input control and sets the
internal oscillator to a fixed frequency operation. The load capac-
itance seen by the external crystal when connected to PINS XIN
and XOUT is equal to 12 pF.
One of the key components to the CY22388, CY22389,
CY22391 family of devices is the analog VCXO. The VCXO is
used to “pull” the reference crystal higher or lower in order to lock
the system frequency to an external source. This is ideal for
applications where the output frequency needs to track along
with an external reference frequency that is constantly shifting.
The VCXO is completely analog, so there is infinite resolution on
the VCXO pull curve. The Analog to Digital Converter steps that
are normally associated with a digital VCXO input is not present
in this device. A special pullable crystal must be used to in order
to have adequate VCXO pull range. Pullable Crystal specifica-
tions are included in this data sheet.
Please refer to the CY22388, CY22389, CY22391 Application
Note for pullable crystal recommendations outside of the
standard industry frequencies given in the Pullable Crystal
Specifications.
VCXO Profile
Figure 4
shows an example of what a VCXO profile looks like.
The analog voltage input is on the X-axis and the PPM range is
on the Y-axis. An increase in the VCXO input voltage results in a
corresponding increase in the output frequency. This has the
effect of moving the PPM from a negative to positive offset.
Figure 4. VCXO Profile
200
150
100
Tuning [ppm
50
0
-50
-100
-150
-200
VCXO input [V]
0
0.5
1
1.5
2
2.5
3
3.5
Absolute Maximum Conditions
Parameter
V
IN
T
S
ESD
HBM
UL-94
MSL
Input Voltage
Temperature, Storage
ESD Protection (Human Body Model)
Flammability Rating
Moisture Sensitivity Level
Description
Condition
Relative to V
SS
Non-Functional
MIL-STD-883, Method 3015
V-0 at 1/8 in.
QFN package
16- and 20-pin TSSOP
Min
–0.5
–0.5
–65
2000
–
3
1
Max
4.6
V
DD
+ 0.5
+125
–
10
Unit
V
VDC
°C
Volts
ppm
V
DD
/AV
DD
/V
DDL
Core Supply Voltage
Pullable Crystal Specifications
[1, 3]
Parameter
F
NOM
C
LNOM
R
1
DL
C
0[2]
Description
13.5 MHz and 27 MHz Crystal AT-Cut
Nominal Load Capacitance
Equivalent Series Resistance (ESR)
Crystal Drive Level
Crystal Shunt Capacitance
Comments
Parallel resonance, Fundamental
mode
Order crystal at one specific C
LNOM
0 ppm
Fundamental mode (CL = Series)
Nominal VDD at 25C over ±120 PPM
Pull Range
Min
Typ.
Max
Unit
See Note 3
11.4
–
–
1.5
12
–
–
3
12.6
40
300
4.0
pF
Ω
μW
pF
Notes
1. Device operates to the following specs, which are guaranteed by design.
2. Increased tolerance available from pull range less than ±120PPM.
3. Refer to CY22388 Application Note and online software for a list of Approved Crystal Specifications.
Document #: 38-07734 Rev. *C
Page 4 of 10
[+] Feedback
CY22388, CY22389, CY22391
Pullable Crystal Specifications
[1, 3]
Parameter
C
1[2]
F
3SEPHI[3]
F
3SEPLO[3]
Description
Crystal Motional Capacitance
Third Overtone Separation from
3*F
NOM
Third Overtone Separation from
3*F
NOM
Mechanical Third (High side of
3*F
NOM
)
Mechanical Third (Low side of
3*F
NOM
)
Comments
Min
12
240
–
Typ.
14
–
–
Max
16.8
–
–120
Unit
fF
ppm
ppm
Recommended Operating Conditions
Parameter
V
DD
/AV
DD
/V
DDL
Operating Voltage
T
A
C
LOAD
t
PU
Ambient Temperature
Maximum Load Capacitance
Power up time for all V
DD
s reach minimum specified voltage (power ramps
must be monotonic)
Description
Min
3.0
–10
–
0.05
Typ.
3.3
–
–
–
Max
3.6
70
15
500
Unit
V
°C
pF
ms
DC Parameters
[4]
Parameter
I
OH[5]
I
OL[5]
I
IH
I
IL
V
IH
V
IL
Parameter
V
VCXO
C
IN
I
VDD
C
INXIN
C
INXTAL
Description
Output High Current
Output Low Current
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
Description
VIN Input Range
Input Capacitance
Supply Current
Input Capacitance at
Crystal
FS0/1/2 and OE Pins only
V
DD
/AV
DD
/V
DDL
Current
VCXO Disabled Fixed Freq. Oscillator
Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3V
V
OL
= 0.5, V
DD
= 3.3V
V
IH
= V
DD
, excluding Vin, Xin
V
IL
= 0V, excluding Vin, Xin
FS0/1/2 OE input CMOS levels
FS0/1/2 OE input CMOS levels
Conditions
Min
12
12
–
–
0.7xA
VDD
–
Min
0
–
–
–
–
Typ.
–
–
5
5
–
–
Typ.
–
–
60
15
12
Max
–
–
10
10
–
0.3xA
VDD
Max
A
VDD
7
–
–
–
Unit
mA
mA
µA
µA
V
V
Unit
V
pF
mA
pF
pF
Input Capacitance at XIN VCXO Disabled External Reference
AC Parameters
Parameter
[4]
1/t1
DC1
Description
Output Frequency
Output Duty Cycle
(excluding REFOUT)
Output Duty Cycle
Conditions
PLL
minmax
/Divider
maximum
Duty Cycle is defined in
Figure 6;
t
2
/t
1
, 50% of V
DD
Duty Cycle is defined in
Figure 6;
t
2
/t
1
, 50% of V
DD
External reference duty cycle between 40% and 60% measured
at V
DD
/2 (Clock output is
≤
125 MHz)
Min
4.2
45
Typ.
–
50
Max Units
166
55
MHz
%
DC2
40
50
60
%
External reference duty cycle between 40% and 60% measured
at V
DD
/2 (Clock output is
>
125 MHz)
DC
REFOUT
Output Duty Cycle
Duty Cycle is defined in
Figure 6;
t
2
/t
1
, 50% of V
DD
(XIN Duty Cycle = 45/55%)
40
50
60
%
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
5. Custom Drive level and is available upon request
Document #: 38-07734 Rev. *C
Page 5 of 10
[+] Feedback
