CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Features
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Functional Description
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
For a complete list of related documentation,
click here.
Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
30-ps maximum output-to-output skew
480-ps maximum propagation delay
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 250 MHz operation
Synchronous clock enable function
20-Pin thin shrunk small outline package (TSSOP) package
2.5-V or 3.3-V operating voltage
[1]
Commercial and industrial operating temperature range
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Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56313 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY2CP1504
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Absolute Maximum Ratings ............................................4
Operating Conditions .......................................................4
DC Electrical Specifications ............................................5
Thermal Resistance ..........................................................5
AC Electrical Specifications ............................................6
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC®Solutions ........................................................14
Cypress Developer Community .................................14
Technical Support ......................................................14
Document Number: 001-56313 Rev. *J
Page 2 of 14
CY2CP1504
Pin Configurations
Figure 1. 20-pin TSSOP Package pinout
Pin Definitions
Pin No.
1
2
3
Pin Name
V
SS
CLK_EN
IN_SEL
Pin Type
Power
Input
Input
Ground
Synchronous clock enable. LVCMOS/low-voltage transistor-transistor logic (LVTTL).
When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, input IN0 is active
When IN_SEL = High, input IN1 is active
LVCMOS input clock. Active when IN_SEL = Low
No connection
Input
Power
Output
Output
LVCMOS input clock. Active when IN_SEL = High
Power supply
LVPECL complementary output clocks
LVPECL output clocks
Description
4
5, 7, 8, 9
6
10, 13, 18
11, 14, 16, 19
12, 15, 17, 20
IN0
NC
IN1
V
DD
Q(0:3)#
Q(0:3)
Input
Document Number: 001-56313 Rev. *J
Page 3 of 14
CY2CP1504
Absolute Maximum Ratings
Parameter
V
DD
V
IN[2]
V
OUT[2]
T
S
ESD
HBM
L
U
UL–94
MSL
Description
Supply voltage
Input voltage, relative to V
SS
Nonfunctional
Nonfunctional
Condition
Min
–0.5
–0.5
Max
4.6
lesser of
4.0 or
V
DD
+ 0.4
lesser of
4.0 or
V
DD
+ 0.4
150
–
Unit
V
V
DC output or I/O voltage, relative Nonfunctional
to V
SS
Storage temperature
Nonfunctional
–0.5
V
–55
2000
°C
V
Electrostatic discharge (ESD)
JEDEC STD 22-A114-B
protection (Human body model)
Latch up
Flammability rating
Moisture sensitivity level
At 1/8 in
Meets or exceeds JEDEC
Spec JESD78B IC latch up test
V-0
3
Operating Conditions
Parameter
V
DD
T
A
t
PU
Description
Supply voltage
Ambient operating temperature
Power ramp time
2.5 V supply
3.3 V supply
Commercial
Industrial
Power-up time for V
DD
to reach minimum
specified voltage (power ramp must be
monotonic)
Condition
Min
2.375
3.135
0
–40
0.05
Max
2.625
3.465
70
85
500
Unit
V
V
°C
°C
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56313 Rev. *J
Page 4 of 14
CY2CP1504
DC Electrical Specifications
(V
DD
= 3.3 V ± 5% or 2.5 V ± 5%; T
A
= 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
I
DD
V
IH1
V
IL1
V
IH2
V
IL2
I
IH
I
IL
V
OH
V
OL
R
P
C
IN
Description
Operating supply current
Input high voltage, All inputs
Input low voltage, All inputs
Input high voltage, All inputs
Input low voltage, All inputs
Input high current, All inputs
Input low current, All inputs
LVPECL output high voltage
LVPECL output low voltage
Internal pull-up/pull-down
resistance
Input capacitance
V
DD
= 3.3 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 2.5 V
Input = V
DD[3]
Input = V
SS[3]
Terminated with 50
to V
DD
– 2.0
[4]
Terminated with 50
to V
DD
– 2.0
[4]
CLK_EN has pull-up only
IN_SEL has pull-down only
Measured at 10 MHz; per pin
Condition
All LVPECL outputs floating (internal I
DD
)
Min
–
2.0
–0.3
1.7
–0.3
–
–150
Max
61
V
DD
+ 0.3
0.8
V
DD
+ 0.3
0.7
150
–
Unit
mA
V
V
V
V
A
A
V
V
k
pF
V
DD
– 1.20 V
DD
– 0.70
V
DD
– 2.0 V
DD
– 1.63
60
–
165
3
Thermal Resistance
Parameter
[5]
θ
JA
θ
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
20-pin TSSOP Unit
80
16
°C/W
°C/W
Notes
3. Positive current flows into the input pin, negative current flows out of the input pin.
4. Refer to
Figure 2 on page 7.
5. These parameters are guaranteed by design and are not tested.
Document Number: 001-56313 Rev. *J
Page 5 of 14
