CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL
®
4-Mbit (256K words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■
■
High speed: 45 ns/55 ns
Ultra-low standby power
❐
Typical standby current: 3.5
A
❐
Maximum standby current: 8.7
A
Embedded ECC for single-bit error correction
[1]
Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
1.0-V data retention
TTL-compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Pb-free 48-ball VFBGA and 44-pin TSOP II packages
devices are accessed by asserting both chip enable inputs – CE
1
as low and CE
2
as HIGH.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O
0
through I/O
15
and
address on A
0
through A
17
pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O
8
through I/O
15
and BLE controls I/O
0
through I/O
7
.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O
0
through I/O
15
).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O
0
through I/O
15
) are placed in a HI-Z state when the
device is deselected (CE HIGH for a single chip enable device
and CE
1
HIGH/CE
2
LOW for a dual chip enable device), or
control signals are deasserted (OE, BLE, BHE).
On the CY62146GE/CY62146GESL devices, the detection and
correction of a single-bit error in the accessed location is
indicated by the assertion of the ERR output (ERR = HIGH)
[2]
.
See
the
Truth
Table
–
CY62146G/CY62146GE/CY62146GSL/CY62146GESL
on
page 17
for a complete description of read and write modes.
The logic block diagrams are on page 2.
■
■
■
■
■
■
Functional Description
CY62146G/CY62146GE and CY62146GSL/CY62146GESL are
high-performance CMOS low-power (MoBL) SRAM devices with
embedded ECC. Both devices are offered in single and dual chip
enable options and in multiple pin configurations. The
CY62146GE/CY62146GESL device includes an ERR pin that
signals an error-detection and correction event during a read
cycle. The CY62146GSL/CY62146GESL
[1]
device supports a
wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V.
Devices with a single chip enable input are accessed by
asserting the chip enable (CE) input LOW. Dual chip enable
Product Portfolio
Product
[3]
Features and
Options
(see the Pin
Configurations
section)
Single or dual
Chip Enables
Power Dissipation
Range
V
CC
Range (V)
Speed (ns)
Operating I
CC
, (mA)
f = f
max
Typ
[4]
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
2.2 V–3.6 V and
4.5 V–5.5 V
55
45
15
15
Max
20
20
Standby, I
SB2
(µA)
Typ
[4]
3.5
3.5
Max
10
8.7
CY62146G(E)18
CY62146G(E)30
CY62146G(E)
Optional ERR
CY62146G(E)SL
[5]
pin
Notes
1. Datasheet specifications are not guaranteed for V
CC
in the range of 3.6 V to 4.5 V.
2. This device does not support automatic write-back on error detection.
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer
Ordering Information
for details.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a V
CC
range of 1.65 V–2.2 V),
V
CC
= 3 V (for V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
5. Datasheet specifications are not guaranteed for V
CC
in the range of 3.6 V to 4.5 V.
Cypress Semiconductor Corporation
Document Number: 001-95420 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 26, 2017
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL
®
Logic Block Diagram – CY62146G/CY62146GSL
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
ROW DECODER
ECC DECODER
SENSE
AMPLIFIERS
MEMORY
ARRAY
I/O
0
‐I/O
7
I/O
8
‐I/O
15
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
BHE
WE
OE
BLE
CE
2
CE
1
Logic Block Diagram – CY62146GE/CY62146GESL
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
ROW DECODER
ECC DECODER
SENSE
AMPLIFIERS
ERR
I/O
0
‐I/O
7
I/O
8
‐I/O
15
MEMORY
ARRAY
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
BHE
WE
OE
BLE
CE
2
CE
1
Document Number: 001-95420 Rev. *E
Page 2 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL
®
Contents
Pin Configuration – CY62146G/CY62146GSL ................ 4
Pin Configuration – CY62146GE ..................................... 6
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
Data Retention Characteristics ..................................... 11
Data Retention Waveform .............................................. 11
AC Switching Characteristics ....................................... 12
Switching Waveforms .................................................... 13
Truth Table – CY62146G/CY62146GE/
CY62146GSL/CY62146GESL ......................................... 17
ERR Output – CY62146GE/CY62146GESL ................... 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-95420 Rev. *E
Page 3 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL
®
Pin Configuration – CY62146G/CY62146GSL
Figure 1. 48-ball VFBGA pinout (Dual Chip Enable without ERR) – CY62146G/CY62146GSL
[6]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Figure 2. 48-ball VFBGA pinout (Single Chip Enable without ERR) – CY62146G/CY62146GSL
[6]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Note
6. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-95420 Rev. *E
Page 4 of 22
CY62146G/CY62146GE
CY62146GSL/CY62146GESL MoBL
®
Pin Configuration – CY62146G/CY62146GSL
(continued)
Figure 3. 44-pin TSOP II pinout (Single Chip Enable without ERR) – CY62146G/CY62146GSL
[7]
A4
A3
A2
A1
A0
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/ WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
44- TSOP-II
Note
7. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 001-95420 Rev. *E
Page 5 of 22
NXP MCU
