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CY62157H30-55ZSXET

静态随机存取存储器

器件类别:半导体    存储器 IC    静态随机存取存储器   

厂商名称:Cypress(赛普拉斯)

器件标准:

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器件参数
参数名称
属性值
厂商名称
Cypress(赛普拉斯)
产品种类
静态随机存取存储器
存储容量
8 Mbit
组织
512 k x 16
访问时间
55 ns
接口类型
Parallel
电源电压-最大
3.6 V
电源电压-最小
2.2 V
电源电流—最大值
36 mA
最小工作温度
- 40 C
最大工作温度
+ 125 C
安装风格
SMD/SMT
封装 / 箱体
TFSOP-48
封装
Reel
存储类型
SDR
系列
CY62157H
工厂包装数量
1000
文档预览
CY62157H MoBL
®
8-Mbit (512K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
Ultra-low standby current
Typical standby current: 5.5A
Maximum standby current: 16
A
High speed: 45 ns
Voltage range: 2.2 V to 3.6 V
Embedded Error-Correcting Code (ECC) for single-bit error
correction
1.0 V data retention
Transistor-transistor logic (TTL) compatible inputs and outputs
Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Data writes are performed by asserting the Write Enable input
(WE LOW), and providing the data and address on device data
(I/O
0
through I/O
15
) and address (A
0
through A
18
) pins
respectively. The Byte High/Low Enable (BHE, BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O
8
through
I/O
15
and BLE controls I/O
0
through I/O
7
.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on I/O lines (I/O
0
through I/O
15
). Byte
accesses can be performed by asserting the required byte
enable signal (BHE, BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O
0
through I/O
15
) are placed in a high impedance state
when the device is deselected (CE
1
HIGH / CE
2
LOW for dual
chip enable device), or control signals are de-asserted (OE, BLE,
BHE).
These devices also have a unique “Byte Power down” feature,
where, if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to standby mode irrespective of the
state of the chip enable(s), thereby saving power.
The CY62157H device is available in a Pb-free 48-ball VFBGA
and 48-pin TSOP I packages. The logic block diagram is on
page 2.
Functional Description
CY62157H is a high-performance CMOS low-power (MoBL)
SRAM device with Embedded Error-Correcting Code. ECC logic
can detect and correct single bit error in accessed location.
This device is offered in dual chip enable option. Dual chip
enable devices are accessed by asserting both chip enable
inputs – CE
1
as LOW and CE
2
as HIGH.
Product Portfolio
Features and
Options
(see the Pin
Configurations
section)
Dual Chip
Enable
Power Dissipation
Range
V
CC
Range (V)
Speed (ns)
Operating I
CC
, (mA)
f = f
max
Typ
[1]
Industrial
2.2 V–3.6 V
45
29
Max
36
Standby, I
SB2
(µA)
Typ
[1]
5.5
Max
16
Product
CY62157H30
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 3 V (for V
CC
range of 2.2 V–3.6 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-88316 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 8, 2018
CY62157H MoBL
®
Logic Block Diagram
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DATA
IN
DRIVERS
ROW DECODER
ECC DECODER
SENSE
AMPLIFIERS
512K x 16
RAM ARRAY
I/O
0
-I/O
7
I/O
8
-I/O
15
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
A18
CE
POWER DOWN
CIRCUIT
BYTE
BHE
BHE
BLE
WE
OE
BLE
CE
2
CE
1
Document Number: 001-88316 Rev. *E
Page 2 of 20
CY62157H MoBL
®
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms ...................................................... 9
Truth Table – CY62157H ................................................ 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Document Number: 001-88316 Rev. *E
Page 3 of 20
CY62157H MoBL
®
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1mm) pinout
[2]
Figure 2. 48-pin TSOP I pinout (Dual Chip Enable)
[2, 3]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE
2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE
1
A0
Notes
2. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
3. Tie the BYTE pin in the 48-pin TSOP I package to V
CC
to use the device as a 1 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8 SRAM by
tying the BYTE signal to V
SS
. In the 2 M × 8 configuration, Pin 45 is the extra address line A20, while BHE, BLE, and I/O
8
to I/O
14
pins are not used and can be left
floating.
Document Number: 001-88316 Rev. *E
Page 4 of 20
CY62157H MoBL
®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential .............................. –0.2 V to V
CC
+ 0.3 V
DC voltage applied to outputs
in High Z state
[4]
................................. –0.2 V to V
CC
+ 0.3 V
DC input voltage
[4]
............................. –0.2 V to V
CC
+ 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Grade
Industrial
Ambient Temperature
–40
C
to +85
C
V
CC
2.2 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range of –40
C
to 85
C
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1[6]
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
[4]
2.2 V to 2.7 V
2.7 V to 3.6 V
2.2 V to 2.7 V
2.7 V to 3.6 V
2.2 V to 2.7 V
2.7 V to 3.6 V
2.2 V to 2.7 V
2.7 V to 3.6 V
Test Conditions
V
CC
= Min, I
OH
= –0.1 mA
V
CC
= Min, I
OH
= –1.0 mA
V
CC
= Min, I
OL
= 0.1 mA
V
CC
= Min, I
OL
= 2.1 mA
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, Output disabled
V
CC
= Max,
I
OUT
= 0 mA,
CMOS levels
f = f
MAX
f = 1 MHz
45 ns
Min
2
2.4
1.8
2
–0.3
–0.3
–1
–1
Typ
[5]
29.0
7.0
5.5
Max
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
+1
36.0
9.0
16.0
A
A
mA
mA
A
V
V
V
Unit
V
Input leakage current
Output leakage current
V
CC
operating supply current
Automatic power down
current – CMOS inputs;
V
CC
= 2.2 to 3.6 V
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V,
(BHE and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V,
f = f
max
(address and data only),
f = 0 (OE, and WE), V
CC
= V
CC(max)
25 °C
[7]
40 °C
[7]
I
SB2[6]
Automatic power down
current – CMOS inputs
V
CC
= 2.2 to 3.6 V
CE
1
> V
CC
– 0.2 V or
CE
2
< 0.2 V,
5.5
6.3
12.0
[7]
6.5
8.0
16.0
A
(BHE and BLE) > V
CC
– 0.2 V, 85 °C
V
IN
> V
CC
– 0.2 V or
V
IN
< 0.2 V,
f = 0, V
CC
= V
CC(max)
Notes
4. V
IL(min)
= –2.0 V and V
IH(max)
= V
CC
+ 2 V for pulse durations of less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 3 V (for V
CC
range of 2.2 V–3.6 V), T
A
= 25 °C.
6. Chip enables (CE
1
and CE
2
) must be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
7. The I
SB2
limits at 25 °C, 70 °C, 40 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
Document Number: 001-88316 Rev. *E
Page 5 of 20
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参数对比
与CY62157H30-55ZSXET相近的元器件有:CY62157H30-55ZSXE。描述及对比如下:
型号 CY62157H30-55ZSXET CY62157H30-55ZSXE
描述 静态随机存取存储器 静态随机存取存储器
厂商名称 Cypress(赛普拉斯) Cypress(赛普拉斯)
产品种类 静态随机存取存储器 静态随机存取存储器
存储容量 8 Mbit 8 Mbit
组织 512 k x 16 512 k x 16
访问时间 55 ns 55 ns
接口类型 Parallel Parallel
电源电压-最大 3.6 V 3.6 V
电源电压-最小 2.2 V 2.2 V
电源电流—最大值 36 mA 36 mA
最小工作温度 - 40 C - 40 C
最大工作温度 + 125 C + 125 C
安装风格 SMD/SMT SMD/SMT
封装 / 箱体 TFSOP-48 TFSOP-48
封装 Reel Tray
存储类型 SDR SDR
系列 CY62157H CY62157H
工厂包装数量 1000 135
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