1
PRELIMINARY
CY7C09349AV
CY7C09359AV
3.3V 4K/8K x 18
Synchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 4K x 18 organization (CY7C09349AV)
— 8K x 18 organization (CY7C09359AV)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 83-MHz
operation
• 0.35-micron CMOS for optimum speed/power
v
• High-speed clock to data access 7.5
[1, 2]
/9/12 ns (max.)
• 3.3V Low operating power
— Active = 135 mA (typical)
— Standby = 10
µA
(typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
•
•
•
•
•
— Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
9
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
9
I/O
9L
–I/O
17L
9
I/O
9R
–I/O
17R
I/O
Control
I/O
Control
9
I/O
0L
–I/O
8L
A
0L
–A
11/12L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[3]
I/O
0R
–I/O
8R
12/13
12/13
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0R
–A
11/12R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[3]
Notes:
1. Call for availability
2. See Page 6 for Load Conditions.
3. A
0
–A
11
for 4K; A
0
–A
12
for 8K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 29, 1999
PRELIMINARY
Functional Description
The CY7C09349AV and CY7C09359AV are high-speed 3.3V
synchronous CMOS 4K and 8K x 18 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
[4]
Reg-
isters on control, address, and data lines allow for minimal set-
up and hold times. In pipelined output mode, data is registered
for decreased cycle time. Clock to data valid t
CD2
= 7.5 ns
[1]
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
CD1
= 18 ns after the
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
CY7C09349AV
CY7C09359AV
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
4. When simultaneously writing to the same location, final value cannot be guaranteed.
2
PRELIMINARY
Pin Configuration
100-Pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
CY7C09349AV
CY7C09359AV
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
[Note 5] A12L
NC
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VCC
FT/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
A8R
A9R
A10R
A11R
A12R
NC
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
[5]
CY7C09359AV (8K x 18)
CY7C09349AV (4K x 18)
A7R
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/10R
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
I/O3L
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O2L
A0L
I/O1L
I/O0L
I/O0R
I/01R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C09349AV
CY7C09359AV
-7
[1, 2]
f
MAX2
(MHz) (Pipelined)
Max Access Time (ns) (Clock to Data, Pipelined)
Typical Operating Current I
CC
(mA)
Typical Standby Current for I
SB1
(mA) (Both Ports TTL Level)
Typical Standby Current for I
SB3
(µA) (Both Ports CMOS Level)
Shaded areas contain advance information.
Note:
5. This pin is NC for CY7C09349AV.
CY7C09349AV
CY7C09359AV
-9
67
9
135
20
10
µA
I/O9R
VCC
GND
GND
VCC
CY7C09349AV
CY7C09359AV
-12
50
12
115
20
10
µA
83
7.5
155
25
10
µA
3
PRELIMINARY
Pin Definitions
Left Port
A
0L
–A
12L
ADS
L
Right Port
A
0R
–A
12R
ADS
R
Description
Address Inputs (A
0
–A
11
for 4K, A
0
–A
12
for 8K devices).
CY7C09349AV
CY7C09359AV
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address
counter with data present on the I/O pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted
to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–I/O
15
for x16 devices).
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte (I/O
0
–I/O
8
for x18, I/O
0
–I/O
7
for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
8/9L
–I/O
15/17L
).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current ..................................................... >200 mA
CE
0L
,CE
1L
CLK
L
CNTEN
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
L
I/O
0L
–I/O
17L
LB
L
CNTRST
R
I/O
0R
–I/O
17R
LB
R
UB
L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
UB
R
OE
R
R/W
R
FT/PIPE
R
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with
Power Applied .............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
CC
+0.5V
DC Input Voltage......................................–0.5V to V
CC
+0.5V
Notes:
6. Industrial parts are available in CY7C09359AV only.
Operating Range
Range
Commercial
Industrial
[6]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±
300 mV
3.3V
±
300 mV
Shaded areas contain advance information.
4
PRELIMINARY
Electrical Characteristics
Over the Operating Range
CY7C09349AV
CY7C09359AV
-7
[1, 2]
Parameter
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
Description
Output HIGH Voltage (V
CC
= Min., I
OH
= –4.0 mA)
Output LOW Voltage (V
CC
= Min., I
OH
= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Operating Current (V
CC
= Max.,
I
OUT
= 0 mA) Outputs Disabled
Standby Current (Both Ports TTL
Level)
[7]
CE
L
& CE
R
≥
V
IH
, f =f
MAX
Com’l.
Ind.
[6]
Com’l.
Ind.
[6]
105
10
95
165
500
125
95
10
85
155
500
115
25
85
20
75
–10
155
2.0
0.8
10
275
–10
135
2.4
0.4
2.0
0.8
10
230
2.4
0.4
-9
CY7C09349AV
CY7C09359AV
-12
2.4
0.4
2.0
0.8
–10
115
155
20
30
85
95
10
10
75
85
10
180
250
70
80
140
150
500
500
100
110
V
V
V
V
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Standby Current (One Port TTL Level)
[7]
Com’l.
CE
L
| CE
R
≥
V
IH
, f =f
MAX
Ind.
[6]
Standby Current (Both Ports CMOS
Com’l.
Level)
[7]
CE
L
& CE
R
≥
V
CC
– 0.2V, f = 0
Ind.
[6]
Standby Current (One Port CMOS
Level)
[7]
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Com’l.
Ind.
[6]
Shaded areas contain advance information.
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Max.
10
10
Unit
pF
pF
Note:
7. CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
AND CE
1
must be asserted to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
5
