• Available in Pb-free and non Pb-free 36-Lead (400-Mil)
Molded SOJ
Functional Description
[1]
The CY7C1049B is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
GND
I/O
2
I/O3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
GND
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512K x 8
ARRAY
I/O
3
I/O
4
I/O
5
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Cypress Semiconductor Corporation
Document #: 38-05169 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 31, 2006
CY7C1049B
Selection Guide
-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Commercial
Industrial
Commercial
L
12
240
8
-
-
-15
15
220
8
-
-
-17
17
195
8
-
0.5
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
4.5V–5.5V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Leakage Current GND < V
I
< V
CC
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l
Com’l
Ind’l
L
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–1
–1
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
240
40
2.2
–0.3
–1
–1
-12
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
220
40
2.2
–0.3
–1
–1
-15
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.3
+1
+1
195
40
-17
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
-
-
8
-
-
8
0.5
8
mA
mA
mA
Note:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
Document #: 38-05169 Rev. *B
Page 2 of 9
CY7C1049B
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤
3 ns
R1 481
Ω
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
≤
3 ns
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05169 Rev. *B
Page 3 of 9
CY7C1049B
Switching Characteristics
Over the Operating Range
[4]
-12
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
V
CC
(typical) to the First Access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[6, 7]
-15
Max.
Min.
1
15
12
15
3
12
6
15
7
0
6
7
3
6
7
0
12
15
15
12
12
0
0
12
8
0
3
6
7
17
12
12
0
0
12
8
0
3
0
3
0
3
Max.
Min.
1
17
-17
Max.
Unit
ms
ns
17
17
8
7
7
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
Description
Min.
1
12
3
0
3
0
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
Write Cycle
[8, 9]
12
10
10
0
0
10
7
0
3
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[10]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Com’l
L V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
Conditions
[11]
Min.
2.0
200
0
t
RC
Max.
Unit
V
µA
ns
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
power
time has to be provided initially before a read/write operation
is started.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
10. t
r
< 3 ns for all the speeds
11. No input may exceed V
CC
+ 0.5V.
Document #: 38-05169 Rev. *B
Page 4 of 9
CY7C1049B
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[13, 14]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
Notes:
12. Device is continuously selected. OE, CE = V
IL
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
