CY7C1471BV25
72-Mbit (2 M × 36)
Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1471BV25, is 2.5 V, 2 M × 36 synchronous flow
through burst SRAMs designed specifically to support unlimited
true back-to-back read or write operations without the insertion
of wait states. The CY7C1471BV25, is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive read or write operations with data transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BW
X
) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tristate control. To avoid bus contention, the output
drivers are synchronously tristated during the data portion of a
write sequence.
For a complete list of related documentation, click
here.
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data transfers on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte Write capability
2.5-V I/O supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous Output Enable (OE)
CY7C1471BV25 available in JEDEC-standard Pb-free 100-pin
TQFP package.
Three Chip Enables (CE
1
, CE
2
, CE
3
) for simple depth
expansion.
Automatic power down feature available using ZZ mode or CE
deselect.
Burst Capability – linear or interleaved burst order
Low standby power
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
305
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-15013 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 11, 2016
CY7C1471BV25
Logic Block Diagram – CY7C1471BV25
A0, A1, A
MODE
CLK
CEN
C
CE
ADDRESS
REGISTER
A1
D1
A0
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1 A1'
A0'
Q0
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
READ LOGIC
E
SLEEP
CONTROL
Document Number: 001-15013 Rev. *N
Page 2 of 22
CY7C1471BV25
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Exit Order ............................................. 19
Boundary Scan Exit Order ............................................. 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ...................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Document Number: 001-15013 Rev. *N
Page 3 of 22
CY7C1471BV25
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) Pinout
BW
D
BW
C
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
OE
ADV/LD
A
82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
81
A
CY7C1471BV25
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
38
39
40
41
42
A1
A0
V
SS
MODE
V
DD
A
A
A
A
43
A
A
A
NC/144M
A
Document Number: 001-15013 Rev. *N
NC/288M
A
A
A
A
A
Page 4 of 22
CY7C1471BV25
Pin Definitions
Name
A
0
, A
1
, A
I/O
Description
Input-
Address Inputs Used to Select One of the Address Locations.
Sampled at the rising edge of the
Synchronous CLK. A
[1:0]
are fed to the two-bit burst counter.
Input-
Byte Write Inputs, Active LOW.
Qualified with WE to conduct writes to the SRAM. Sampled on the
BW
A
, BW
B
,
BW
C
, BW
D
Synchronous rising edge of CLK.
WE
ADV/LD
Input-
Write Enable Input, Active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
Input-
Advance/Load Input.
Used to advance the on-chip address counter or load a new address. When HIGH
Synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
Input-
Clock
Clock Input.
Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is only
recognized if CEN is active LOW.
CLK
CE
1
CE
2
CE
3
OE
Input-
Chip Enable 1 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
Synchronous and CE
3
to select or deselect the device.
Input-
Chip Enable 2 Input, Active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
3
to select or deselect the device.
Input-
Chip Enable 3 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
2
to select or deselect the device.
Input-
Output Enable, Asynchronous Input, Active LOW.
Combined with the synchronous logic block inside
Asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input-
Clock Enable Input, Active LOW.
When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “Sleep” Input.
This active HIGH input places the device in a non-time-critical “sleep” condition with
Asynchronous data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull down.
I/O-
Bidirectional Data I/O Lines.
As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
s
and DQP
X
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to DQ
s
. During write
Synchronous sequences, DQP
X
is controlled by BW
X
correspondingly.
Input Strap Pin
Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to V
DD
or left floating selects interleaved
burst sequence.
Power Supply
Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Ground
–
Power Supply for the I/O Circuitry.
Ground for the Device.
No Connects.
Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
CEN
ZZ
DQ
s
DQP
X
MODE
V
DD
V
DDQ
V
SS
NC
Document Number: 001-15013 Rev. *N
Page 5 of 22
