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CY7C4201V/4211V/4221VCY7C4241V/4251VLow Voltage 256/512/1K/4K/8K x 9 Synchronous FIFOs
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Low Voltage 256/512/1K/4K/8K x 9 Syn-
chronous FIFOs
Features
■
■
■
32-pin PLCC
Available in Pb-Free Packages
High-speed, low-power, first-in, first-out (FIFO) memories
❐
256 x 9 (CY7C4201V)
❐
512 x 9 (CY7C4211V)
❐
1K x 9 (CY7C4221V)
❐
4K x 9 (CY7C4241V)
❐
8K x 9 (CY7C4251V)
High-speed 66-MHz operation (15-ns read/write cycle time)
Low power (I
CC
= 20 mA)
3.3V operation for low power consumption and easy integration
into low-voltage systems
5V-tolerant inputs V
IH max
= 5V
Fully asynchronous and simultaneous read and write operation
Empty, Full, and Programmable Almost Empty and
Almost Full status flags
TTL compatible
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground pins for reduced noise
Width expansion capability
Space saving 32-pin 7 mm × 7 mm TQFP
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a Free-Running Clock (WCLK) and two Write Enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a Free-Running Read Clock (RCLK) and two Read
Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an
Output Enable Pin (OE). The Read (RCLK) and Write (WCLK)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic to
direct the flow of data.
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 19, 2010
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Contents
Features............................................................................. 1
Functional Description..................................................... 1
Logic Block Diagram........................................................ 1
Contents ............................................................................ 2
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 3
Pin Definitions .................................................................. 3
Functional Description......................................................
4
Architecture ...................................................................... 4
Resetting the FIFO............................................................ 4
FIFO Operation ................................................................. 4
Programming .................................................................... 5
Programmable Flag (PAE, PAF) Operation ................ 6
Width Expansion Configuration...................................... 7
Flag Operation .................................................................. 7
Full Flag....................................................................... 7
Empty Flag .................................................................. 7
Maximum Ratings............................................................. 8
Operating Range............................................................... 8
Electrical Characteristics
Over the Operating Range ..... 8
Capacitance ...................................................................... 8
Switching Characteristics
Over the Operating Range .... 9
Switching Waveforms .................................................... 10
Ordering Information...................................................... 16
256 x 9 Low Voltage Synchronous FIFO................... 16
512 x 9 Low Voltage Synchronous FIFO................... 16
1K x 9 Low Voltage Synchronous FIFO .................... 16
4K x 9 Low Voltage Synchronous FIFO .................... 16
8K x 9 Low Voltage Synchronous FIFO .................... 16
Package Diagrams.......................................................... 17
Document History Page ................................................. 19
Worldwide Sales and Design Support....................... 19
Products .................................................................... 19
PSoC Solutions ......................................................... 19
Document #: 38-06010 Rev. *C
Page 2 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Pin Configuration
Figure 1. 32-Pin PLCC
Figure 2. 32-Pin TQFP
Top View
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
14151617 181920
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
Selection Guide
Description
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current
CY7C4421V
Density
64 x 9
Commercial
CY7C4201V
256 x 9
CY7C4211V
512 x 9
CY7C42X1V-15
66.7
11
15
4
1
10
20
CY7C4221V
1K x 9
CY7C42X1V-25
40
15
25
6
1
15
20
CY7C4231V
2K x 9
CY7C42X1V-35
28.6
20
35
7
2
20
20
CY7C4241V
4K x 9
Unit
MHz
ns
ns
ns
ns
ns
mA
CY7C4251V
8K x 9
Pin Definitions
Signal Name
D
0−8
Q
0−8
WEN1
Description
Data Inputs
Data Outputs
Write Enable 1
I/O
I
O
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is
HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable.
If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable
flag-offset register.
Description
WEN2/LD
Dual Mode Pin
Write Enable 2
Load
I
I
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I
I
Document #: 38-06010 Rev. *C
Page 3 of 19
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CY7C4201V/4211V/4221V
CY7C4241V/4251V
Pin Definitions
(continued)
Signal Name
RCLK
Description
Read Clock
I/O
I
Description
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty.
When WEN2/LD is LOW, RCLK reads data out of the programmable flag
offset register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
Resets device to empty condition.
A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
EF
FF
PAE
PAF
RS
OE
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
O
O
O
O
I
I
Functional Description
The CY7C42X1V provides four status pins: Empty, Full, Almost Empty,
Almost Full. The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to Empty-7 and
Full-7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle
All configurations are fabricated using an advanced 0.65μ P-Well
CMOS technology. Input ESD protection is greater than 2001V, and
latch-up is prevented by the use of guard rings.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D
0-8
pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will be
presented on the Q
0-8
outputs. New data will be presented on
each rising edge of RCLK while REN1 and REN2 are active.
REN1 and REN2 must set up t
ENS
before RCLK for it to be a valid
read function. WEN1 and WEN2 must occur t
ENS
before WCLK
for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q
0-8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q
0-8
outputs after t
OE
.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0-8
outputs even
after additional reads occur.
Write Enable 1 (WEN1).
If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1) is
LOW, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored is the RAM array sequentially and independently
of any on-going read operation.
Write Enable 2/Load (WEN2/LD).
This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows for depth expansion. If
Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset
(RS=LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK.)
Data is stored in the RAM array sequentially and independently
of any on-going read operation.
Architecture
The CY7C42X1V consists of an array of 64 to 8K words of nine
bits each (implemented by a dual-port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF.)
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
0-8
) go LOW t
RSF
after the
rising edge of RS. In order for the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW. All flags are guaranteed to be valid t
RSF
after RS is taken LOW.
Document #: 38-06010 Rev. *C
Page 4 of 19
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