PRELIMINARY
CYWB0224ABS, CYWB0224ABM
CONFIDENTIAL
CYWB0226ABS, CYWB0226ABM
West Bridge™: Astoria™ USB and Mass
Storage Peripheral Controller
Features
•
N-Xpress™ NAND controller technology
• Interleave up to 16 NANDs with 8 chip enables (CE#) for
x8 or x16 SLC (CYWB0224ABS) or MLC
(CYWB0224ABM) NAND Flash devices
• 4-bit error correction coding
• Bad block management
• Static wear leveling
• Pseudo NAND Flash interface
• SPI (slave mode) interface
• DMA slave support
•
Multimedia device support
• Up to 2 SD, SDIO, MMC, MMC+, and CE-ATA devices
•
•
•
•
•
Ultra low power, 1.8V core operation
Low power modes
Small footprint, 6x6mm VFBGA
Supports I2C boot and processor boot
Selectable clock input frequencies
• 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz
•
SLIM™
architecture, allowing simultaneous and
independent data paths between the processor and USB,
and between the USB and mass storage
Applications
•
•
•
•
•
•
•
•
Cellular Phones
Portable Media Players
Personal Digital Assistants
Portable Navigation Devices
Digital Cameras
POS Terminals
Portable Video Recorders
Data Cards and Wireless Dongles
•
High speed USB at 480 Mbps
• USB 2.0 compliant
• Integrated USB switch
• Integrated USB 2.0 transceiver, smart serial interface en-
gine
• 16 programmable endpoints
•
Flexible processor interface, which supports:
• Multiplexing and nonmultiplexing address and data inter-
face
• SRAM interface
• Pseudo CRAM interface (Antioch interface)
Block Diagram
West Bridge
TM
Astoria
TM
Control
Registers
Flexible Processor
Interface
uC
Access Control
P
High-Speed
USB 2.0 XCVR
U
SLIM
TM
SD/SDIO/
MMC+/ CE-
ATA Block
Cypress
N-Xpress
TM
Engine
Configurable Storage
Interface
S
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
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CYWB0226ABS, CYWB0226ABM
to 66.7 MBps. Synchronous accesses can be performed at 33
MHz across 16 bits for up to 66.7 MBps bandwidth.
The memory address is decoded to access any of the multiple
endpoint buffers inside Astoria. These endpoints serve as buffers
for data between each pair of ports, for example, between the
processor port and the USB port. The processor writes and reads
into these buffers via the memory interface.
Access to these buffers is controlled by either using a DMA
protocol or using an interrupt to the main processor. These two
modes are configurable by the external processor.
As a DMA slave, Astoria generates a DMA request signal to
signify to the main processor that a specific buffer is ready to be
read from or written to. The external processor monitors this
signal and polls Astoria for the specific buffers ready for read or
write. It then performs the appropriate read or write operations
on the buffer through the processor interface. This way, the
external processor only deals with the buffers to access a
multitude of storage devices connected to Astoria.
In the Interrupt mode, Astoria communicates important buffer
status changes to the external processor using an interrupt
signal. The external processor then polls Astoria for the specific
buffers ready for read or write, and it performs the appropriate
read or write operations through the processor interface.
Functional Overview
The
SLIM™
Architecture
The Simultaneous Link to Independent Multimedia (SLIM) archi-
tecture allows three different interfaces (P-port, S-port and
U-port) to connect to one another independently.
With this architecture, connecting a device using Astoria to a PC
through USB does not disturb any of the functions of the device.
The device can still access mass storage at the same time the
PC is synchronizing with the main processor.
The SLIM architecture enables new usage models in which a PC
can access a mass storage device independent of the main
processor, or enumerate access to both the mass storage and
the main processor at the same time.
In a handset, this typically enables using the phone as a thumb
drive, downloading media files to the phone while still having full
functionality available on the phone, or using the same phone as
a modem to connect the PC to the web.
8051 Microprocessor
The 8051 microprocessor embedded in Astoria does basic trans-
action management for all the transactions between P-Port,
S-Port, and U-Port. The 8051 does not reside in the data path; it
manages the path. The data path is optimized for performance.
The 8051 executes firmware that supports NAND, SD, SDIO,
MMC+, and CE-ATA devices at the S-Port. For the NAND device,
the 8051 firmware follows the smart media algorithm to support:
USB Interface (U-Port)
In accordance with the USB 2.0 specification, Astoria can
operate in Full Speed USB mode in addition to High Speed USB.
The USB interface consists of the USB transceiver. The USB
interface is accessible by both the P-Port and the S-Port.
The Astoria USB interface supports programmable
CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints.
Astoria also has an integrated USB switch shown in
Figure 1
that
allows interfacing to an external Full Speed USB PHY.
Figure 1. U-Port With Switch and Control Block
SWD+
UVALID
USBALLO
•
•
•
•
Physical to logical management
Four random bits ECC detection and correction support
Wear leveling
NAND Flash bad blocks handling
Configuration and Status Registers
The West Bridge Astoria device includes configuration and
status registers that are accessible as memory mapped registers
through the processor interface. The configuration registers
allow the system to specify certain behavior of Astoria. For
example, it is able to mask certain status registers from raising
an interrupt. The status registers convey various status, such as
the addresses of buffers for read operations.
SWD-
USB Switch
and Control
Block
USB 2.0
XCVR
USB Port
(U Port)
D+
D-
Processor Interface (P-Port)
Communication with the external processor is realized through a
dedicated processor interface. This interface is configured to
support different interface standards. This interface supports
multiplexing and nonmultiplexing address or data bus in both
synchronous and asynchronous pseudo CRAM-mapped, and
nonmultiplexing address or data asynchronous SRAM-mapped
memory accesses. The interface also can be configured to a
pseudo NAND interface to support the processor’s NAND
interface. In addition, this interface can be configured to support
SPI slave. Asynchronous accesses can reach a bandwidth of up
Mass Storage Support (S-Port)
The S-Port is configurable in six different interface modes, either
simultaneously supporting an SD/SDIO/MMC+/CE-ATA port and
a 8-bit SLC or MLC NAND Flash ports, supporting two
SD/SDIO/MMC+/CE-ATA ports, supporting up to eight Chip
Enable (CE#) for 8-bit or 16-bit SLC or MLC NAND Flash port,
supporting SD/SDIO/MMC+/CE-ATA port and GPIO, supporting
NAND Flash port and GPIO, and GPIO. These configurations
are controlled by the 8051 firmware. The 16-bit NAND Flash
interface can only be used when there is no other mass storage
device connected to the S-Port.
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embedded 8051 sets up reading and writing transaction of the
NAND along with its required protocols. It performs standard
NAND management functions such as ECC and wear leveling.
The Astoria supports single bit ECC for the SLC and four bytes
random ECC detection and correction for MLC NAND Flash.
SLC NAND Flash devices are supported by CYWB0244ABS.
CYWB0244ABM supports both SLC and MLC NAND Flash
devices.
SD/SDIO/MMC+/CE-ATA Port (S-Port)
When Astoria is configured with firmware to support SD, SDIO,
MMC+, and CE-ATA, this interface supports:
N-Xpress™ NAND Controller (S-Port)
Astoria, as part of its mass storage management functions, fully
manages the SLC and MLC NAND Flash devices. The
embedded 8051 manages the actual reading and writing of the
NAND along with its required protocols. It performs standard
NAND management functions such as ECC and wear leveling.
The Astoria supports single bit ECC for the SLC and 4-bit ECC
for MLC NAND Flash. SLC NAND Flash devices are supported
by CYWB0244ABS. CYWB0244ABM supports both SLC and
MLC NAND Flash devices.
S-Port Configuration Modes
The S Port is configurable in six different interface modes.
•
•
•
•
•
•
•
The Multimedia Card System Specification, MMCA Technical
Committee, Version 4.1.
NAND Flash and SD/SDIO/MMC/CE-ATA interface mode
NAND Flash interface mode
Dual SD/SDIO/MMC/CE-ATA interface mode
SD/SDIO/MMC/CE-ATA and GPIO interface mode
NAND Flash and GPIO interface mode
GPIO interface mode
•
SD Memory Card Specification - Part 1, Physical Layer Speci-
fication, SD Group, Version 1.10, October 15, 2004.
•
SD Memory Card Specification - Part 1, Physical Layer Speci-
fication, SD Group, Version 2.0, May 9, 2006.
•
SD Specifications - Part E1 SDIO Specification, Version 1.10,
August 18, 2004.
NAND Flash Interface Mode
The NAND Flash interface mode configures the S-Port to
interface with NAND Flash devices only. In this interface mode,
the S-Port is configured to interface up to sixteen 8-bit SLC or
MLC NAND Flash
NAND Port (S-Port)
Astoria, as part of its mass storage management functions, fully
manages the SLC and MLC NAND Flash devices. The
•
CE-ATA Specification - CE-ATA Digital Protocol, CE-ATA
Committee, Version 1.1, September, 2005.
West Bridge Astoria provides support for 1-bit and 4-bit SD and
SDIO cards, 1-bit, 4-bit and 8-bit MMC, MMC+ cards, and
CE-ATA drive. For the SD, SDIO, MMC/MMC Plus, and CE-ATA,
this block supports one card for one physical bus interface.
Astoria supports SD commands including the multisector
program command that are handled by the API.
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CYWB0226ABS, CYWB0226ABM
Pin Assignments
Table 1. Astoria Pin Assignments
Pin Name
PCRAM Non
Multiplexing
CLK (pull low
in Asyn mode)
CE#
IO
PCRAM
Multiplexing
(ADM)
CLK (pull -low in
Async mode)
CE#
IO
SRAM
IO
PNAND
IO
SPI
IO
Pin De-
scription
Clock
Chip
Enable/PNA
ND Chip
Select/SPI
Slave Select
Addr. Bus
0/PNAND
Command
Latch
Addr. Bus
1/PNAND
Ready_Buy
Addr. Bus
[3:2]
Addr. Bus
4/PNAND
Write
Protect
Addr. Bus
5/I2C clock
Addr. Bus
6/I2C data
Addr. Bus 7
SPI
Input/Data
Bus 0
SPI
Output/Data
Bus 1
Data Bus
Address
Valid
Output
Enable
Write
Enable
Interrupt
Request
DMA
Request
DMA
Acknowl-
edgement
USB D+
USB D-
USB Switch UVDDQ
UVSSQ
DP
USB Switch
DM
GVDDQ
VGND
Power
Domain
I
I
I
I
Ext pull low
CE#
I
I
Ext pull low
CE#
I
I
SCK
SS#
I
I
A0
I
Ext pull-up
I
A0
I
CLE
I
Ext pull-up
I
A1
I
Ext pull-up
I
A1
I
RB#
O
Ext pull-up
I
A[3:2]
I
A[2] = 1
A[3] = don’t
care
Ext pull-up
I
A[3:2]
I
A[3:2] = 00
I
A[3:2] = 10
I
P-Port
A4
I
I
A4
I
WP#
I
Ext pull-up
I
A5
A6
A7
DQ[0]
I
I
I
SCL
SDA
Ext pull-up
IO A5
IO A6
I
A7
I
I
I
SCL
SDA
A7 => 1:SBD
A7 => 0: LBD
IO
IO
I
IO
SCL
SDA
Ext pull-up
SDI
IO
IO
I
I
PVDDQ
VGND
IO AD[0]
IO DQ[0]
IO IO[0]
DQ[1]
IO AD[1]
IO DQ[1]
IO IO[1]
IO
SDO
O
DQ[15:2]
ADV#
OE#
WE#
INT#
IO AD[15:2]
I
I
I
O
O
I
ADV#
OE#
WE#
INT#
DRQ#
DACK#
IO DQ[15:2]
I
I
I
O
O
I
OE#
WE#
INT#
DRQ#
DACK#
IO IO[15:2]
I
I
I
ALE
RE#
WE#
IO
I
I
I
O
O
I
Ext pull-up
Ext pull-up
Ext pull-up
Ext pull-up
SINT#
N/C
Ext pull-up
I
I
I
I
O
O
I
O INT#
O DRQ#
I
DACK#
DRQ &
Int
DRQ#
DACK#
D+
IO/Z
IO/Z
IO/Z
IO/Z
U-Port
D-
SWD+
SWD-
Page 4 of 7
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CYWB0224ABS, CYWB0224ABM
CYWB0226ABS, CYWB0226ABM
Table 1. Astoria Pin Assignments
(continued)
SDIO & NAND
Configuration IO
SD_D[7:0]
NAND only
Configuration
IO
Double SDIO
Configuration IO
NAND & GPIO
Configuration
IO
IO
SDIO & GPIO
Configuration
SD_D[7:0]
IO
IO
GPIO only
Configuration
PD[7:0] (GPIO)
IO
IO
SD Data
bus/NAND
Upper IO
bus
SD Clock,
NAND CE8#
or NAND
R/B4#
SD
Command,
NAND CE7#
or NAND
R/B4#
SD Power
Control/NA
ND CE6#
GPIO (SD
Write
Protection
Microswitch
) or NAND
CE5#
NAND
Lower IO
bus
CMD Latch
Enable
Address
Latch
Enable
Chip Enable SNVD-
DQ
Read
VGND
Enable
Write
Enable
Write
Protect
Ready/Busy
Chip Enable
2
RESET
OUT or
NAND
Busy/Ready
General
Input/Output
0 or
SD/MMC
Card
Detection or
NAND CE4# GVDDQ
VGND
General
Input/Output
1,
NAND
CE3#, or
SD2_CD
RESET
Wake Up
Signal
Clock Select
0 and 1
GVDDQ
Test Config- VGND
uration
Crystal/Cloc
XVDDQ
k IN
VGND
Crystal Out
SSVD-
DQ
VGND
IO NAND_IO[15:8] IO SD_D[7:0]
or PD[7:0]
(GPIO)
O
NAND_CE8# or
NAND_R/B4#
O
I
SD_CLK
IO NAND_IO[15:8]
or
PD[7:0] (GPIO)
O PC-7 (GPIO) or
NAND_CE8# or
NAND_R/B4#
IO PC-3 (GPIO) or
NAND_CE7# or
NAND_R/B3#
SD_CLK
IO
O
I
IO
O
I
SD_CLK
PC-7 (GPIO)
IO
SD_CMD
IO NAND_CE7# or
NAND_R/B3#
O
I
SD_CMD
SD_CMD
IO
PC-3 (GPIO)
IO
SD_POW
O
NAND_CE6#
O
SD_POW
PC-6 (GPIO) or
NAND_CE6#
I
PC-5 (GPIO) or
NAND_CE5#
IO
O
IO
SD_POW
PC-6 (GPIO)
IO
SD_WP
I
NAND_CE5#
O
SD_WP
SD_WP
I
N/C
I
S-Port
NAND_IO[7:0]
IO NAND_IO[7:0]
IO SD2_D[7:0]
IO NAND_IO[7:0]
O
PB[7:0] (GPIO)
IO
PB[7:0] (GPIO)
IO
NAND_CLE
NAND_ALE
O
O
NAND_CLE
NAND_ALE
O
O
SD2_CLK
SD2_CMD
O NAND_CLE
IO NAND_ALE
O
O
PA-6 (GPIO)
PA-7 (GPIO)
IO
IO
PA-6 (GPIO)
PA-7 (GPIO)
IO
IO
NAND_CE#
NAND_RE#
NAND_WE#
NAND_WP#
NAND_R/B#
NAND_CE2#
RESETOUT /
NAND_R/B2#
O
O
O
O
I
O
O
I
NAND_CE#
NAND_RE#
NAND_WE#
NAND_WP#
NAND_R/B#
NAND_CE2#
NAND_R/B2#
O
O
O
O
I
O
I
SD2_POW
N/C
N/C
PA-5 (GPIO)
N/C
SD2_WP
RESETOUT
O NAND_CE#
O NAND_RE#
O NAND_WE#
IO NAND_WP#
I
NAND_R/B#
O
O
O
I
I
O
0
I
PC-0 (GPIO)
N/C
N/C
PA-5 (GPIO)
N/C
PC-2 (GPIO)
RESETOUT
IO
O
O
IO
I
IO
O
PC-0 (GPIO)
N/C
N/C
PA-5 (GPIO)
N/C
PC-2 (GPIO)
RESETOUT
IO
O
O
IO
I
IO
O
O NAND_CE2#
O RESETOUT or
NAND_R/B2#
PC-4
(GPIO[0]) /
SD_CD /
NAND_CE4#
IO NAND_CE4#
I
O
O
PC-4 (GPIO[0]) IO PC-4 (GPIO[0])
/
or
SD_CD
I NAND_CE4#
IO
O
PC-4 (GPIO[0])
or
SD_CD
IO
I
PC-4 (GPIO[0])
IO
Other
PC-5
(GPIO[1]) /
NAND_CE3#
IO NAND_CE3#
O
O
PC-5 (GPIO[1]) IO PC-5 (GPIO[1])
/
or
SD2_CD
I NAND_CE3#
IO
O
PC-5 (GPIO[1])
IO
PC-5 (GPIO[1])
IO
RESET#
WAKEUP
XTALSLC[1:0]
TEST[2:0]
XTALIN
XTALOUT
I
I
I
I
I
O
Clock
Conf
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