DA14531
Ultra Low Power Bluetooth 5.1 SoC
Final
General Description
The DA14531 is an ultra-low power SoC integrating a 2.4 GHz transceiver and an Arm® Cortex-M0+
microcontroller with a RAM of 48 kB and a One-Time Programmable (OTP) memory of 32 kB. It can
be used as a standalone application processor or as a data pump in hosted systems.
The radio transceiver, the baseband processor, and the qualified Bluetooth® low energy stack is fully
compliant with the Bluetooth® Low Energy 5.1 standard.
The DA14531 has dedicated hardware for the Link Layer implementation of BLE and interface
controllers for enhanced connectivity capabilities.
The BLE firmware includes the L2CAP service layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT), and the Generic Access Profile (GAP). All
profiles published by the Bluetooth® SIG as well as custom profiles are supported.
The device is suitable for disposables, wireless sensor nodes, beacons, proximity tags and trackers,
smart HID devices (stylus, keyboards, mice, and trackpads), toys, and medical and industrial
applications.
Key Features
■
Compatible with Bluetooth v5.1, ETSI EN 300
■
Clocks
328 and EN 300 440 Class 2 (Europe), FCC
□
32 MHz crystal and 32 MHz RC osc.
CFR47 Part 15 (US) and ARIB STD-T66
□
32 kHz crystal and 32/512 kHz RC osc.
(Japan)
□
15 kHz RCX as crystal replacement
■
Supports up to three BLE connections
■
Programmable Reset Circuitry
■
Typical cold boot to radio active 35 ms
■
2× General purpose Timers with capture and
■
Processing power
□
16 MHz 32-bit Arm
®
Cortex-M0+ with
SWD interface
PWM capabilities
□
18300 EEMBC IoTMark-BLE
®
score
□
Dedicated Link Layer and AES-128
Encryption Processor
□
Software-based True Random Number
Generator (TRNG)
■
Memories
□
32 kB One-Time-Programmable (OTP)
□
48 kB Retainable System RAM
□
144 kB ROM
■
Power management
□
Integrated Buck/Boost DCDC converter
□
Buck: 1.1 V ≤ V
BAT_HIGH
≤ 3.3 V (min 1.8V if
OTP read needed)
■
Digital interfaces
□
GPIOs: 6 (WLCSP17), 12 (FCGQFN24)
□
2× UARTs (one with flow control)
□
SPI Master/Slave up to 32 MHz (Master)
□
I2C bus at 100 kHz and 400 kHz
□
3-axis capable Quadrature Decoder
□
Keyboard controller
■
Analog interfaces
□
4-channel 10-bit ADC
■
Radio transceiver
□
Fully integrated 2.4 GHz CMOS
transceiver
□
Boost: 1.1 V ≤ V
BAT_LOW
≤ 1.65 V
□
Clock-less hibernation mode: Buck 270
nA, Boost 240 nA
□
Single wire antenna
□
TX: 3.5 mA, RX: 2.2 mA (system currents
with DC-DC, V
BAT_HIGH
=3 V and 0 dBm)
□
Programmable transmit output power from
-19.5 dBm to +2.5 dBm
□
Built-in temperature sensor for die
temperature monitoring
□
-94 dBm receiver sensitivity
■
Packages:
□
WLCSP 17 balls, 1.7 × 2.05, 0.5 mm pitch
□
FCGQFN 24 pins, 2.2 × 3, 0.4 mm pitch
Revision 3.0
1 of 374
Datasheet
CFR0011-120-00
12-Mar-2020
© 2020 Dialog Semiconductor
DA14531
Ultra Low Power Bluetooth 5.1 SoC
Final
Applications
■
Medical applications
■
Disposables
■
Beacons
■
Proximity tags and trackers
■
Wireless sensor nodes
□
Fitness trackers
□
Consumer health
■
Smartwatches
■
Human interface devices (HID)
□
Stylus pens
□
Keyboards
□
Mouse devices
□
Trackpads
■
Toys
■
Industrial appliances
Key Benefits
■
Lowest power consumption
■
Smallest system size
■
Lowest system cost
System Diagram
Figure 1: System Diagram
Datasheet
CFR0011-120-00
Revision 3.0
2 of 374
12-Mar-2020
© 2020 Dialog Semiconductor
DA14531
Ultra Low Power Bluetooth 5.1 SoC
Final
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 2
Key Benefits ......................................................................................................................................... 2
System Diagram .................................................................................................................................. 2
Contents ............................................................................................................................................... 3
Figures .................................................................................................................................................. 9
Tables ................................................................................................................................................. 10
1
2
Block Diagram ............................................................................................................................. 19
Packages and Pinout .................................................................................................................. 20
2.1 WLCSP17 ........................................................................................................................... 20
2.2 FCGQFN24 ......................................................................................................................... 24
Specifications .............................................................................................................................. 28
3.1 Absolute Maximum Ratings ................................................................................................ 30
3.2 Recommended Operating Conditions ................................................................................. 30
3.3 DC Characteristics .............................................................................................................. 31
3.4 Timing Characteristics......................................................................................................... 33
3.5 RCX Oscillator ..................................................................................................................... 33
3.6 XTAL32MHz Oscillator ........................................................................................................ 34
3.7 XTAL32kHz Oscillator ......................................................................................................... 34
3.8 RC32MHz Oscillator ............................................................................................................ 35
3.9 DC-DC Converter ................................................................................................................ 35
3.10 LDO_LOW Characteristics .................................................................................................. 36
3.11 Digital I/O Characteristics.................................................................................................... 37
3.12 Power On Reset .................................................................................................................. 39
3.13 GP ADC .............................................................................................................................. 39
3.14 Temperature Sensor ........................................................................................................... 41
3.15 Radio ................................................................................................................................... 41
System Overview ......................................................................................................................... 46
4.1 Internal Blocks..................................................................................................................... 46
4.2 Power Management Unit..................................................................................................... 47
4.2.1
Introduction .......................................................................................................... 47
4.2.2
Architecture .......................................................................................................... 47
4.2.2.1
Digital Power Domains .................................................................... 49
4.2.2.2
Power Modes ................................................................................... 50
4.2.2.3
VDD Level in Hibernation ................................................................ 53
4.2.2.4
Retainable Registers ....................................................................... 53
4.2.3
Programming ....................................................................................................... 53
4.2.3.1
Buck Configuration .......................................................................... 53
4.2.3.2
Boost Configuration ......................................................................... 54
4.2.3.3
Bypass Configuration....................................................................... 55
4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep) .............................................................. 56
Revision 3.0
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Datasheet
CFR0011-120-00
12-Mar-2020
© 2020 Dialog Semiconductor
DA14531
Ultra Low Power Bluetooth 5.1 SoC
Final
4.4
4.5
5
4.3.1
Power-up/Wake-up in Buck Configuration........................................................... 56
4.3.2
Power-up/Wake-up in Boost Configuration ......................................................... 58
4.3.3
Go-to-Sleep and Refresh Bandgap ..................................................................... 59
OTP Memory Layout ........................................................................................................... 60
4.4.1
OTP Header ......................................................................................................... 60
4.4.2
Configuration Script ............................................................................................. 62
BootROM Sequence ........................................................................................................... 63
Reset ............................................................................................................................................. 67
5.1 Introduction ......................................................................................................................... 67
5.2 Architecture ......................................................................................................................... 67
5.2.1
POR, HW, and SW Reset .................................................................................... 67
5.2.2
POR Functionality ................................................................................................ 69
5.2.2.1
POR Timer Clock ............................................................................. 69
5.2.2.2
RST Pad .......................................................................................... 69
5.2.2.3
POR from GPIO ............................................................................... 69
5.2.3
POR Timing Diagram ........................................................................................... 69
5.2.4
POR Considerations ............................................................................................ 70
5.3 Programming ....................................................................................................................... 70
Arm Cortex-M0+........................................................................................................................... 71
6.1 Introduction ......................................................................................................................... 71
6.2 Architecture ......................................................................................................................... 72
6.2.1
Interrupts .............................................................................................................. 72
6.2.2
System Timer (systick) ........................................................................................ 74
6.2.3
Wake-Up Interrupt Controller ............................................................................... 74
6.3 Programming ....................................................................................................................... 74
AMBA Bus .................................................................................................................................... 75
7.1 Introduction ......................................................................................................................... 75
7.2 Architecture ......................................................................................................................... 75
7.3 Programming ....................................................................................................................... 76
Memory Map................................................................................................................................. 77
Memory Controller ...................................................................................................................... 79
9.1 Introduction ......................................................................................................................... 79
9.2 Architecture ......................................................................................................................... 79
9.2.1
Arbitration ............................................................................................................ 80
6
7
8
9
10 Clock Generation ......................................................................................................................... 81
10.1 Clock Tree ........................................................................................................................... 81
10.1.1 General Clock Constraints ................................................................................... 83
10.2 Crystal Oscillators ............................................................................................................... 83
10.2.1 Frequency Control (32 MHz Crystal) ................................................................... 83
10.2.2 Automated Trimming and Settling Notification .................................................... 84
10.3 RC Oscillators ..................................................................................................................... 85
10.3.1 Frequency Calibration.......................................................................................... 86
11 OTP Controller ............................................................................................................................. 87
11.1 Introduction ......................................................................................................................... 87
11.2 Architecture ......................................................................................................................... 87
Datasheet
CFR0011-120-00
Revision 3.0
4 of 374
12-Mar-2020
© 2020 Dialog Semiconductor
DA14531
Ultra Low Power Bluetooth 5.1 SoC
Final
11.2.1 OTP Accessing Considerations ........................................................................... 89
11.3 Programming ....................................................................................................................... 89
12 DMA Controller ............................................................................................................................ 90
12.1 Introduction ......................................................................................................................... 90
12.2 Architecture ......................................................................................................................... 90
12.2.1 DMA Peripherals .................................................................................................. 90
12.2.2 Input/Output Multiplexer....................................................................................... 91
12.2.3 DMA Channel Operation...................................................................................... 91
12.2.4 DMA Arbitration ................................................................................................... 92
12.2.5 Freezing DMA Channels...................................................................................... 93
12.3 Programming ....................................................................................................................... 93
12.3.1 Memory to Memory Transfers.............................................................................. 93
12.3.2 Peripheral to Memory Transfers .......................................................................... 93
13 I2C Interface ................................................................................................................................. 95
13.1 Introduction ......................................................................................................................... 95
13.2 Architecture ......................................................................................................................... 95
13.2.1 I2C Bus Terms ..................................................................................................... 96
13.2.1.1
Bus Transfer Terms ......................................................................... 97
13.2.2 I2C Behavior ........................................................................................................ 97
13.2.2.1
START and STOP Generation ........................................................ 98
13.2.2.2
Combined Formats .......................................................................... 98
13.2.3 I2C Protocols ....................................................................................................... 98
13.2.3.1
START and STOP Conditions ......................................................... 98
13.2.3.2
Addressing Slave Protocol .............................................................. 99
13.2.3.3
Transmitting and Receiving Protocols ........................................... 100
13.2.4 Multiple Master Arbitration ................................................................................. 101
13.2.5 Clock Synchronization ....................................................................................... 102
13.3 Programming ..................................................................................................................... 103
14 UART ........................................................................................................................................... 105
14.1 Introduction ....................................................................................................................... 105
14.2 Architecture ....................................................................................................................... 106
14.2.1 UART (RS232) Serial Protocol .......................................................................... 106
14.2.2 Clock Support .................................................................................................... 107
14.2.3 Interrupts ............................................................................................................ 107
14.2.4 Programmable THRE Interrupt .......................................................................... 108
14.2.5 Shadow Registers .............................................................................................. 110
14.2.6 Direct Test Mode ............................................................................................... 110
14.3 Programming ..................................................................................................................... 110
15 SPI Interface ............................................................................................................................... 112
15.1 Introduction ....................................................................................................................... 112
15.2 Architecture ....................................................................................................................... 113
15.2.1 SPI Timing ......................................................................................................... 113
15.3 Programming ..................................................................................................................... 114
15.3.1 Master Mode ...................................................................................................... 114
15.3.2 Slave Mode ........................................................................................................ 115
Datasheet
CFR0011-120-00
Revision 3.0
5 of 374
12-Mar-2020
© 2020 Dialog Semiconductor
