DA14583
Bluetooth Low Energy 4.2 SoC with Flash Memory
General Description
FINAL
AES-128 bit encryption Processor
Memories
The DA14583 integrated circuit has a fully integrated
1 Mbit Flash memory
radio transceiver and baseband processor for
Blue-
32 kB One-Time-Programmable (OTP) memory
tooth
®
low energy.
It can be used as a standalone
42 kB System SRAM
application processor or as a data pump in hosted sys-
84 kB ROM
tems.
8 kB Retention SRAM
Power management
The DA14583 supports a flexible memory architecture,
Integrated Buck mode DC-DC converter
including 1 Mbit of Flash memory, for storing Bluetooth
Embedded charge pump for Flash programming
profiles and custom application code, which can be
P0, P1, and P2 ports with 3.3 V tolerance
updated over the air (OTA). The qualified
Bluetooth low
Supports coin (typ. 3.0 V) battery cells
energy
protocol stack is stored in a dedicated ROM. All
®
Cortex
®
-M0 processor via
10-bit ADC for battery voltage measurement
software runs on the ARM
Digital controlled oscillators
a simple scheduler.
16 MHz crystal (±20 ppm max) and RC oscillator
The
Bluetooth low energy
firmware includes the
32 kHz crystal (±50 ppm, ±500 ppm max) and
L2CAP service layer protocols, Security Manager
RCX oscillator
(SM), Attribute Protocol (ATT), the Generic Attribute
General purpose, Capture and Sleep timers
Profile (GATT) and the Generic Access Profile (GAP).
Digital interfaces
All profiles published by the Bluetooth SIG as well as
24 general purpose I/Os
custom profiles are supported.
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
The transceiver interfaces directly to the antenna and
I2C bus at 100 kHz, 400 kHz
is fully compliant with the
Bluetooth 4.2
standard.
3-axes capable Quadrature Decoder
The DA14583 has dedicated hardware for the Link
Analog interfaces
Layer implementation of
Bluetooth low energy
and
4-channel 10-bit ADC
interface controllers for enhanced connectivity capabili-
Radio transceiver
ties.
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
Features
switching required
Complies with
Bluetooth V4.2,
ETSI EN 300 328 and
Supply current at VBAT3V:
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
0 dBm transmit output power
(US) and ARIB STD-T66 (Japan)
Processing power
-20 dBm output power in “Near Field Mode”
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
-93 dBm receiver sensitivity
Packages:
face
Dedicated Link Layer Processor
QFN 40 pins, 5 mm x 5 mm
________________________________________________________________________________________________
System Diagram
Datasheet
CFR0011-120-01
Revision 3.0
1 of 150
04-Nov-2016
© 2014 Dialog Semiconductor
DA14583
Bluetooth Low Energy 4.2 SoC with Flash Memory
Contents
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 7
4 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 8
4.2 BLUETOOTH LOW ENERGY . . . . . . . . . . . . . . 8
4.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . . 9
4.2.3 SmartSnippets
4.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . .11
4.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . .11
4.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.6.3 I2C Interface . . . . . . . . . . . . . . . . . . . . . 12
4.6.4 General Purpose ADC . . . . . . . . . . . . . . 12
4.6.5 Quadrature Decoder . . . . . . . . . . . . . . . 12
4.6.6 Keyboard Controller . . . . . . . . . . . . . . . . 12
4.6.7 Input/Output Ports . . . . . . . . . . . . . . . . . 12
4.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7.1 General Purpose Timers . . . . . . . . . . . . 13
4.7.2 Wake-Up Timer . . . . . . . . . . . . . . . . . . . 13
4.7.3 Watchdog Timer. . . . . . . . . . . . . . . . . . . 13
4.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 14
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . 148
7.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 148
7.2 SOLDERING INFORMATION . . . . . . . . . . . . 148
7.3 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 149
FINAL
Datasheet
CFR0011-120-01
Revision 3.0
2 of 150
04-Nov-2016
© 2014 Dialog Semiconductor
DA14583
Bluetooth Low Energy 4.2 SoC with Flash Memory
1
Block Diagram
FINAL
24 April 2012
ARM Cortex M0
XTAL
32.768 kHz
XTAL
16 MHz
DCDC
(BUCK/BOOST)
LDO
SYS
LDO
RET
LDO
LDO
LDO
SYS
SYS
RF
RC
16 MHz
RC
32 kHz
RCX
CORE
BLE Core
POReset
SWD (JTAG)
System/
Exchange
RAM
42 kB
AES-128
LINK LAYER
HARDWARE
Radio
Transceiver
Memory Controller
Ret. RAM2
3 kB
Ret. RAM3
2 kB
Ret. RAM4
1 kB
APB bridge
Ret. RAM
2 kB
POWER/CLOCK
Management (PMU)
KEYBOARD
CTRL
QUAD
DECODER
WAKE UP
TIMER
SW TIMER
GP ADC
OTP
32 kB
ROM
84 kB
DMA
OTPC
Timer 0
1x PWM
Timer 2
3x PWM
SPI
FLASH
1 Mbit
UART2
UART
FIFO
FIFO
FIFO
FIFO
GPIO MULTIPLEXING
Figure 1: DA14583 Block Diagram
Datasheet
CFR0011-120-01
Revision 3.0
3 of 150
SPI
I2C
04-Nov-2016
© 2014 Dialog Semiconductor
DA14583
Bluetooth Low Energy 4.2 SoC with Flash Memory
2
Pinout
The pin/ball assignment is depicted in the following fig-
ure:
The DA14583 comes in a Quad Flat Package No
Leads (QFN) with 40 pins.
FINAL
P2_0/SPI_CLK
P2_9/SPI_DI
40
39
38
37
36
35
34
33
32
P0_0
P0_1
P0_2
P0_3
VCC_FLASH
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
VDCDC_RF
RFIOm
RFIOp
P2_8
P2_6
P2_7
P2_5
VPP
XTAL16Mm
XTAL16Mp
P1_3
P1_2
SW_CLK
SWDIO
P1_1
VBAT1V
P1_0
SWITCH
DA14583
(Top View)
27
26
25
24
23
22
21
VBAT_RF
XTAL32Kp
VBAT3V
P2_2
P2_3/SPI_EN
XTAL32Km
Pin 0: GND
plane
Figure 2: QFN40 Pin Assignment
Datasheet
CFR0011-120-01
Revision 3.0
4 of 150
P2_4/SPI_DO
RST
VDCDC
GND
04-Nov-2016
© 2014 Dialog Semiconductor
DA14583
Bluetooth Low Energy 4.2 SoC with Flash Memory
FINAL
Table 1: Pin Description
Pin Name
Type
Drive
(mA)
Reset
State
(Note 1)
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
Description
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4/SW_CLK
P1_5/SWDIO
P2_0/SPI_CLK
P2_1
P2_2
P2_3/SPI_EN
P2_4/SPI_DO
P2_5
P2_6
P2_7
P2_8
P2_9/SPI_DI
P3_0 to P3_7
Debug Interface
SWDIO/P1_5
SW_CLK/P1_4
Clocks
XTAL16Mp
XTAL16Mm
XTAL32kp
XTAL32km
QD_CHA_X
QD_CHB_X
QD_CHA_Y
QD_CHB_Y
QD_CHA_Z
QD_CHB_Z
SPI Bus Interface
SPI_CLK/P2_0
SPI_DI/P2_9
SPI_DO/P2_4
DO
DI
DO
INPUT/OUTPUT. SPI Clock.
Shall not be remapped.
INPUT. SPI Data input.
Shall not be remapped.
OUTPUT. SPI Data output.
Shall not be remapped.
AI
AO
AI
AO
DI
DI
DI
DI
DI
DI
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
INPUT. Channel A for the X axis. Mapped on Px ports
INPUT. Channel B for the X axis. Mapped on Px ports
INPUT. Channel A for the Y axis. Mapped on Px ports
INPUT. Channel B for the Y axis. Mapped on Px ports
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
DIO
DIO
4.8
4.8
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
4.8
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
4.8
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
Note: During the boot sequence, the four SPI pins of port P2
are used to access the internal Flash memory. Therefore
these pins shall not be remapped or used for any other pur-
pose.
Not supported
4.8
4.8
Quadrature Decoder
Datasheet
CFR0011-120-01
Revision 3.0
5 of 150
04-Nov-2016
© 2014 Dialog Semiconductor
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