DA7210
Ultra-low power stereo codec
Company confidential
General description
The DA7210 is a high fidelity audio codec with integrated true-ground capless headphone driver
suitable for a variety of low power, digital portable audio products.
Featuring a high efficiency headphone amplifier and supporting economic single supply voltages
down to 1.8 V, the ultra-low 2.5 mW power consumption extends music playback time for battery
operated equipment.
Eight analogue input pins allow multiple audio sources to be internally mixed, eliminating the need for
external switches. Both single-ended and fully-differential line and microphone inputs are supported
with built-in variable gain amplifiers to optimise dynamic range prior to digitisation.
DA7210 provides simultaneous connection to stereo headphone, stereo line outputs, and a mono
differential output. Stereo line outputs can be differential or single-ended. Both stereo outputs have
volume control from -54 dB to +15 dB.
Filtering and gain control is performed digitally including 5-band EQ and a digital input AGC with
programmable attack and decay parameters. A configurable signal processing engine allows various
enhancements and effects on the digital audio signal like acoustic filtering, wind noise suppression
and 3D sound.
The multi-slot I2S/PCM interface supports all common sample rates between 8 and 96 kHz in master
or slave mode operation.
Key features
■
Stereo multi-bit Delta Sigma DAC with SNR
100 dB ('A' weighted @ 48 kHz)
■
Audio serial data bus supports I2S,
left/right justified, DSP and TDM modes
■
Stereo multi-bit Delta Sigma ADC with SNR
96 dB ('A' weighted @ 48 kHz)
■
Stereo or mono differential microphone
interface
■
Ultra low-power stereo headphone driver with
■
Programmable ultra-low noise bias supply for
electret microphones
□
Stereo DAC to HP playback power:
2.5 mW
■
Volume controlled stereo auxiliary inputs and
outputs supporting FM Radio and fixed gain
□
2x58 mW output power (16 Ω)
speaker amplifiers
□
‘Capless’ output via GND centred signals
■
Multi-mode audio routing and mixers
□
Four level charge pump with continuous
■
Pop & click suppression circuitry
tracking of audio signal (Class G)
■
ASSP DSP filter engine for digital audio
□
Short circuit protection
■
Support of 8, 11.025, 12, 16, 22.05, 24, 32,
44.1, 48 and 96 kHz sample rates
enhancements (acoustic filtering, wind noise
suppression, 5-band equaliser, 3D sound,
automatic gain control)
(1.8/2.5 V)
■
On-chip PLL with signal shaper and audio
Sample Rate Matching
■
Supports supply from single voltage
■
Extensive modular power control
■
Package: 49 bump WL-CSP – 0.4 mm pitch
■
Wide range of external clocks including
industry standard 256xFs, system clock 12,
13, 24, 26 or 27 MHz and low power 32 kHz
mode
Applications
■
Personal media players
■
Portable consumer devices
■
Music handsets
■
Personal navigation devices
Datasheet
CFR0011-120-00 Rev 5
Revision 3a
1 of 113
15-Oct-2015
© 2015 Dialog Semiconductor
DA7210
Ultra-low power stereo codec
Company confidential
Contents
General description ............................................................................................................................. 1
Key features ......................................................................................................................................... 1
Applications ......................................................................................................................................... 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 3
Tables ................................................................................................................................................... 4
1
2
3
4
5
6
7
Terms and definitions ................................................................................................................... 8
Block diagram ................................................................................................................................ 9
Pinout ........................................................................................................................................... 10
3.1 The 49-ball DA7210 device ................................................................................................. 13
Absolute maximum ratings ........................................................................................................ 14
Recommended operating conditions ........................................................................................ 14
Electrical characteristics ............................................................................................................ 15
Timing characteristics ................................................................................................................ 23
7.1 Digital audio interface timing - I2S/DSP (in master/slave mode) ........................................ 23
7.2 Digital audio control timing - 2-wire control timing .............................................................. 24
7.3 Digital audio interface timing - 4-wire control timing ........................................................... 25
Functional description ................................................................................................................ 26
8.1 Stereo codec ....................................................................................................................... 26
8.1.1
Input signal chain ................................................................................................. 26
8.1.2
Microphone inputs ............................................................................................... 27
8.1.3
Auxiliary inputs ..................................................................................................... 27
8.1.4
Stereo audio ADC ................................................................................................ 28
8.1.5
Automatic level control (ALC) .............................................................................. 30
8.1.6
Noise gate ............................................................................................................ 32
8.2 Output signal chain ............................................................................................................. 32
8.2.1
Stereo audio DAC ................................................................................................ 32
8.2.2
Soft mute ............................................................................................................. 33
8.2.3
Output mixer and line-out amplifier ...................................................................... 34
8.2.4
Headphone amplifier ............................................................................................ 37
8.2.5
Ambient noise suppression ................................................................................. 38
8.2.6
Digital signal processing engine .......................................................................... 38
8.3 Programming the general purpose filter .............................................................................. 40
8.4 Hi-Fi recording ..................................................................................................................... 41
8.4.1
5-band equaliser for recording path ..................................................................... 41
8.4.2
Digital audio processing for the record path ........................................................ 44
8.5 Hi-Fi playback ..................................................................................................................... 45
8.5.1
5-band equaliser for playback path ..................................................................... 45
8.5.2
Digital audio processing for playback path .......................................................... 45
8.6 Telephone/Bluetooth voice recording/playback at low sample rates .................................. 47
8.6.1
Voice filtering for recording at low sample rates .................................................. 47
8.6.2
Voice filtering for playback at low sample rates .................................................. 48
8.6.3
Digital audio processing for phone applications .................................................. 50
Revision 3a
2 of 113
8
Datasheet
CFR0011-120-00 Rev 5
15-Oct-2015
© 2015 Dialog Semiconductor
DA7210
Ultra-low power stereo codec
9
Company confidential
INTERFACES................................................................................................................................ 51
9.1 Digital audio interface (DAI) ................................................................................................ 51
9.1.1
Operation modes DAI interface ........................................................................... 51
9.1.2
Right justified mode ............................................................................................. 52
9.1.3
Left justified mode................................................................................................ 52
9.1.4
I2S mode ............................................................................................................. 52
9.1.5
DSP mode ........................................................................................................... 53
9.1.6
TDM mode ........................................................................................................... 53
9.1.7
Clocking schemes................................................................................................ 53
9.1.8
Master mode ........................................................................................................ 55
9.1.9
Programming master and 32 kHz mode – PLL enabled ..................................... 57
9.2 Slave mode ......................................................................................................................... 59
9.2.1
Conditions: ........................................................................................................... 59
9.2.2
Programming slave mode – PLL not enabled ..................................................... 59
9.2.3
Programming slave mode – PLL enabled ........................................................... 61
9.2.4
32 kHz master or slave mode .............................................................................. 63
9.2.5
Phase locked loop (PLL)...................................................................................... 63
9.2.6
Control interface .................................................................................................. 64
9.2.7
4-wire communication .......................................................................................... 65
9.2.8
2-wire communication .......................................................................................... 66
9.2.9
Details of the 2-wire control bus protocol ............................................................ 67
10 Register definitions ..................................................................................................................... 69
10.1 Register map ....................................................................................................................... 69
10.2 Control and status registers ................................................................................................ 72
10.3 Codec registers .................................................................................................................. 74
10.4 GP filter engine ................................................................................................................... 96
10.5 ALC level controls ............................................................................................................. 107
11 Package information ................................................................................................................. 110
11.1 Package outlines ............................................................................................................... 110
11.2 Soldering information ........................................................................................................ 110
12 Ordering information ................................................................................................................ 110
13 Applications information .......................................................................................................... 111
13.1 Supporting information ...................................................................................................... 111
13.2 Minimum component recommendations ........................................................................... 111
13.3 General component suggestions ...................................................................................... 112
Figures
Figure 1: DA7210 block diagram ........................................................................................................... 9
Figure 2: DA7210 pad arrangement (bottom view ball side up) .......................................................... 10
Figure 3: DA7210 power supply topology ........................................................................................... 13
Figure 4: I2S/DSP timing diagram ....................................................................................................... 23
Figure 5: 2-wire control timing diagram ............................................................................................... 24
Figure 6: 4-wire control timing diagram ............................................................................................... 25
Figure 7: Typical microphone applications .......................................................................................... 27
Figure 8: ADC and DAC DC blocking (cut-off frequency setting ‘00’ to ‘11’, 16 kHz) ......................... 29
Figure 9: ADC pass band attenuation (audio mode, 48 kHz).............................................................. 29
Datasheet
CFR0011-120-00 Rev 5
Revision 3a
3 of 113
15-Oct-2015
© 2015 Dialog Semiconductor
DA7210
Ultra-low power stereo codec
Company confidential
Figure 10: ADC pass band suppression (audio mode, 48 kHz) .......................................................... 30
Figure 11: Operation of ALC................................................................................................................ 30
Figure 12: DAC DC blocking (cut-off frequency setting ‘00’ to ‘11’, 48 kHz) ....................................... 33
Figure 13: DAC pass band attenuation (audio mode, 48 kHz)............................................................ 34
Figure 14: DAC pass band suppression (audio mode, 48 kHz) .......................................................... 34
Figure 15: DA7210 audio signal paths ................................................................................................ 36
Figure 16: Digital signal processing engine (simplified block diagram) .............................................. 39
Figure 17: Direct form I implementation of a second order IIR filter ................................................... 39
Figure 18: Band 5 (LP 50 Hz) frequency response at FS = 48 kHz .................................................... 42
Figure 19: Band 5 (BP 150 Hz) frequency response at FS = 48 kHz ................................................. 42
Figure 20: Band 5 (BP 500 Hz) frequency response at FS = 48 kHz ................................................. 43
Figure 21: Band 5 (BP 2500 Hz) frequency response at FS = 48 kHz ............................................... 43
Figure 22: Band 5 (HP 5000 Hz) frequency response at FS = 48 kHz ............................................... 43
Figure 23: Record only ........................................................................................................................ 44
Figure 24: Record with sound monitor ................................................................................................ 44
Figure 25: Stereo playback (for example, freefield headphone equalisation) ..................................... 45
Figure 26: Sound spatialiser for stereo speaker ................................................................................. 46
Figure 27: Voice mode recording high-pass filter (cut-off frequency setting ‘000’ to ‘111’, 8 kHz) .... 47
Figure 28: Voice mode recording frequency response (setting ‘001’, 8 kHz) ..................................... 48
Figure 29: Voice mode recording stop band suppression (8 kHz) ...................................................... 48
Figure 30: Voice mode playback high-pass filter (cut-off frequency setting ‘000’ to ‘111’, 16 kHz) ... 49
Figure 31: Voice mode playback frequency response (setting ‘001’, 8 kHz) ...................................... 49
Figure 32: Voice mode playback stop band suppression (8 kHz) ....................................................... 50
Figure 33: Transmit (red), receive (green) and sidetone (blue) sound filtering for phone applications
............................................................................................................................................................. 50
Figure 34: Right justified format .......................................................................................................... 52
Figure 35: Left justified format ............................................................................................................. 52
Figure 36: I2S format ........................................................................................................................... 52
Figure 37: DSP format ......................................................................................................................... 53
Figure 38: TDM left justified format ..................................................................................................... 53
Figure 39: TDM DSP format ................................................................................................................ 53
Figure 40: PLL master mode start up sequence ................................................................................. 58
Figure 41: Non-PLL mode start-up sequence ..................................................................................... 61
Figure 42: PLL Slave mode start-up sequence ................................................................................... 63
Figure 43: PLL block diagram.............................................................................................................. 64
Figure 44: Schematic of a 4-wire and a 2-wire control bus ................................................................. 64
Figure 45: 4-wire host write and read timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘1’’) ................... 66
Figure 46: 2-wire byte write (SI/DATA line) ......................................................................................... 67
Figure 47: Examples of 2-wire byte read (SI/DATA line) .................................................................... 67
Figure 48: Examples of 2-wire page read (SI/DATA line) ................................................................... 68
Figure 49: 2-wire page write (SI/DATA line) ........................................................................................ 68
Figure 50: 2-wire repeated write (SI/DATA line) ................................................................................. 68
Figure 51: 49 bump WL-CSP 0.4mm pitch package outline drawing ............................................... 110
Tables
Table 1: Pin description ....................................................................................................................... 10
Table 2: Pin type definition .................................................................................................................. 12
Table 3: Absolute maximum ratings .................................................................................................... 14
Table 4: Recommended operating conditions ..................................................................................... 14
Table 5: Power dissipation table ......................................................................................................... 15
Table 6: Electrical characteristics: Microphone bias ........................................................................... 16
Table 7: Electrical characteristics: Input mixing units .......................................................................... 16
Table 8: Electrical characteristics: Analogue to digital converter (ADC) ............................................. 17
Table 9: Electrical characteristics: Digital to analogue converter (DAC) ............................................. 18
Table 10: Electrical characteristics: Line out and receiver amplifier ................................................... 19
Table 11: Electrical characteristics: Line out amplifier ........................................................................ 20
Table 12: Electrical characteristics: Dynamic charge pump ................................................................ 20
Datasheet
CFR0011-120-00 Rev 5
Revision 3a
4 of 113
15-Oct-2015
© 2015 Dialog Semiconductor
DA7210
Ultra-low power stereo codec
Company confidential
Table 13: Electrical characteristics: Headphone amplifier .................................................................. 21
Table 14: Electrical characteristics: Phase locked loop (MCLK) ......................................................... 22
Table 15: Electrical characteristics: Digital I/O .................................................................................... 22
Table 16: I2S/DSP timing characteristics ............................................................................................ 23
Table 17: 2-wire control timing characteristics .................................................................................... 24
Table 18: 4-wire control timing characteristics .................................................................................... 25
Table 19: Start-up times after setting SC_MST_EN = 1 ..................................................................... 25
Table 20: ADC digital high pass filter specifications ........................................................................... 28
Table 21: Permitted register values for ALC_NOIS (0x85 [5:0]) ......................................................... 31
Table 22: DAC digital high pass filter specifications ........................................................................... 33
Table 23: Headphone/OUT1 amplifier gain settings ........................................................................... 37
Table 24: GP filter section enable bits ................................................................................................. 41
Table 25: Band-equaliser corner frequencies ..................................................................................... 41
Table 26: 5-band-equaliser turn-over/centre frequencies ................................................................... 41
Table 27: Voice mode recording high-pass filter specifications .......................................................... 47
Table 28: Voice mode playback high-pass filter specifications ........................................................... 49
Table 29: Internal system clock frequency .......................................................................................... 54
Table 30: Block enable and system standby bits ................................................................................ 54
Table 31: ADC and DAC clock frequencies ........................................................................................ 55
Table 32: Master mode PLL-DIV look up table ................................................................................... 56
Table 33: SRM mode PLL-DIV look up table ...................................................................................... 56
Table 34: PLL master mode register setting recommendations.......................................................... 57
Table 35: MCLK frequencies in non-PLL slave mode ......................................................................... 59
Table 36: Non-PLL slave mode and PLL master mode sample rate settings ..................................... 60
Table 37: SRM mode PLL division ratio settings ................................................................................ 62
Table 38: Slave mode PLL-enabled register setting recommendations ............................................. 62
Table 39: 4 wire interface .................................................................................................................... 65
Table 40: 4 wire clock configurations .................................................................................................. 66
Table 41: Register map ....................................................................................................................... 69
Table 42: PAGE0 0x00 ........................................................................................................................ 72
Table 43: CONTROL 0x01 .................................................................................................................. 72
Table 44: STATUS 0x02...................................................................................................................... 72
Table 45: STARTUP 1 0x03 ................................................................................................................ 73
Table 46: STARTUP 2 0x04 ................................................................................................................ 73
Table 47: STARTUP 3 0x05 ................................................................................................................ 74
Table 48: MIC_L 0x07 ......................................................................................................................... 74
Table 49: MIC_R 0x08......................................................................................................................... 75
Table 50: AUX1_L 0x09 ...................................................................................................................... 75
Table 51: AUX1_R 0x0A ..................................................................................................................... 75
Table 52: AUX2 0x0B .......................................................................................................................... 76
Table 53: IN_GAIN 0x0C ..................................................................................................................... 77
Table 54: INMIX_L 0x0D ..................................................................................................................... 78
Table 55: INMIX_R 0x0E ..................................................................................................................... 78
Table 56: ADC_HPF 0x0F ................................................................................................................... 79
Table 57: ADC 0x10 ............................................................................................................................ 79
Table 58: ADC_EQ1_2 0x11 ............................................................................................................... 80
Table 59: ADC_EQ3_4 0x12 ............................................................................................................... 81
Table 60: ADC_EQ5 0x13 ................................................................................................................... 82
Table 61: DAC_HPF 0x14 ................................................................................................................... 83
Table 62: DAC_L 0x15 ........................................................................................................................ 83
Table 63: DAC_R 0x16........................................................................................................................ 84
Table 64: DAC_SEL 0x17 ................................................................................................................... 84
Table 65: SOFTMUTE 0x18 ................................................................................................................ 85
Table 66: DAC_EQ1_2 0x19 ............................................................................................................... 86
Table 67: DAC_EQ3_4 0x1A .............................................................................................................. 87
Table 68: DAC_EQ5 0x1B................................................................................................................... 88
Table 69: OUTMIX_L 0x1C ................................................................................................................. 88
Table 70: OUTMIX_R 0x1D................................................................................................................. 89
Table 71: OUT1_L 0x1E ...................................................................................................................... 89
Datasheet
CFR0011-120-00 Rev 5
Revision 3a
5 of 113
15-Oct-2015
© 2015 Dialog Semiconductor
Microchip MCU
