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DEI1022-G

Line Driver, 2 Func, 2 Driver, BIPolar, PDSO14, GREEN, MS-012AB, SOIC-14

器件类别:模拟混合信号IC    驱动程序和接口   

厂商名称:Device Engineering Incorporated

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
SOIC
包装说明
SOP,
针数
14
Reach Compliance Code
compliant
ECCN代码
EAR99
差分输出
YES
驱动器位数
2
输入特性
STANDARD
接口集成电路类型
LINE DRIVER
接口标准
ARINC 429
JESD-30 代码
R-PDSO-G14
JESD-609代码
e4
长度
8.636 mm
湿度敏感等级
1
标称负供电电压
-15 V
功能数量
2
端子数量
14
最高工作温度
85 °C
最低工作温度
-55 °C
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
260
认证状态
Not Qualified
最大接收延迟
座面最大高度
1.7526 mm
最大供电电压
5.25 V
最小供电电压
4.75 V
标称供电电压
5 V
电源电压1-最大
16.5 V
电源电压1-分钟
11.4 V
电源电压1-Nom
15 V
表面贴装
YES
技术
BIPOLAR
温度等级
OTHER
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
40
最大传输延迟
3000 ns
宽度
3.9116 mm
Base Number Matches
1
文档预览
Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1022, DEI1023
DEI1024, DEI1025
ARINC 429 Line Driver
Integrated Circuit
Features:
ARINC 429 Line Driver for high speed (100KHz) and
low speed (12.5KHz) data rates.
Adjustable Slew rates via external capacitors.
Small foot print (14L SOIC NB)
Programmable output differential range via V
REF
pin.
Drives full ARINC load of 400
and 0.03
µ
F.
-55ºC to +85ºC operating temperature range.
100% Final testing.
Functional Description:
The ARINC 429 Line Driver Circuit is a bipolar monolithic IC designed to meet the requirements of several general aviation serial data bus
standards. These include the differential bipolar RZ types such as ARINC 429, ARINC 571, and ARINC 575.
The DEI1022, DEI1023, DEI1024, and DEI1025 are a family of ARINC Line Driver circuits with variations in driver output
resistance and output fusing. See the Product Matrix definition table below to find the correct version for your application.
Serial data is presented on DATA(A) and DATA(B) logic inputs in the dual rail format of the DEI1016. The driver is enabled by the SYNC
and CLOCK inputs. The output voltage level is programmed by the V
REF
input and is normally tied to +5VDC along with V
1
to produce
output levels of +5 volts, 0 volts, and -5 volts on each output for ±10 volts differential outputs.
The driver output resistance of the DEI1022 and DEI1023 is 75
Ω ±20%
at room temperature; 37.5
on each output. The driver output resistance
of the DEI1024 and the DEI1025 is zero. The output slew rate is controlled
by external timing capacitors on C
A
and C
B
. Typical values are 75pF for
100KHz and 500pF for 12.5KHz data.
Figure 1: Pinout Diagram
©2008 Device Engineering Incorporated
Page
1 of 10
DS-MW-01022-01 Rev. C
7/21/09
Pin #
1
2
3
13
4
12
5
11
6
10
7
8
9
14
Pin Name
V
REF
NC
SYNC
CLOCK
Table 2: Pin Descriptions
Analog Input. The voltage on V
REF
sets the output voltage levels on A
OUT
and B
OUT
. The output logic levels
swing between +V
REF
, 0 volts, and –V
REF
volts.
No Connect
Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission.
Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission.
DATA(A) Logic inputs. These signals contain the Serial Data to be transmitted on the ARINC 429 data bus. Refer to
DATA(B) Figure 3.
C
A
C
B
A
OUT
B
OUT
−V
GND
+V
V
1
Analog Nodes. External timing capacitors are tied from these points to ground to establish the output signal slew
rate. Typical C
A
= C
B
= 75pF for 100 kHz data and C
A
= C
B
= 500pF for 12.5 kHz data. *
Outputs. These are the line driver outputs which are connected to the aircraft serial data bus.
Negative Supply Input. –15VDC nominal.
Ground.
Positive Supply Input. +15VDC nominal.
Logic Supply Input. +5VDC nominal.
Any electronic switching of the capacitor on the pins must not inhibit the full voltage swings.
*
C
A
and C
B
pin voltages swing between
±5
volts.
Table 3: Truth Table
INPUTS
SYNC
NOTE 1
OUTPUTS
NOTE 1
CLOCK
NOTE 1
DATA(A)
X
X
L
H
H
L
DATA(B)
NOTE 1
A
OUT
0
0
0
0
+V
REF
−V
REF
B
OUT
0
0
0
0
−V
REF
+V
REF
COMMENTS
NULL
NULL
NULL
NULL
LOGIC 1
LOGIC 0
L
X
H
H
H
H
NOTES:
1.
X
L
H
H
H
H
X
X
L
H
L
H
X = Don’t Care
Figure 2: Block Diagram
©2008 Device Engineering Incorporated
Page
2 of 10
DS-MW-01022-01 Rev. C
7/21/09
Table 4: Absolute Maximum Ratings
PARAMETER
Voltage between pins +V and –V
V
1
Maximum Voltage
V
REF
Maximum Voltage
Logic Inputs
Peak Body Temperature
Non-G Part
-G Part
Storage Temperature
Max Junction Temperature
Die Limit (short term operation)
Max Junction Temperature
Plastic Package Limit (prolonged operation)
Output Short Circuit Duration
Output Over-Voltage Protection
Power Dissipation
-
T
STG
T
J
T
J
MAX1
SYMBOL
V
1
V
REF
RATING
40
7
6
(GND-0.3V) to
(V1 + 0.3V)
240
260
-65 to +150
+175
+145
UNITS
V
V
V
V
o
o
o
C
C
C
C
MAX2
o
See Note 1
See Note 2
See Table 6
Notes:
1. One output at a time can be shorted to ground indefinitely. Both outputs can be shorted indefinitely to ground or to each
other for
T
A
< 45° C and Data Duty Cycle < 40%.
2. Both DEI1023 and DEI1025 outputs are fused at between 0.5 Amp DC and 1.0 Amp DC to prevent an over-voltage fault
from coupling onto the system power bus. The DEI1022 and DEI1024 outputs are not fused. External fusing must be
provided to meet the Transmitter Fault Isolation of the ARINC 429 Specification.
Table 5: Operating Range
PARAMETER
Positive Supply Voltage
Negative Supply Voltage
V
1
V
REF
(For ARINC 429)
V
REF
(For other applications)
Operating Temperature
SYMBOL
+V
-V
V
1
V
REF
V
REF
T
A
MIN
+11.4
-11.4
+4.75
+4.75
+3
-55
+5
+5
TYP
MAX
+16.5
-16.5
+5.25
+5.25
+6
+85
UNITS
VDC
VDC
VDC
VDC
VDC
°C
Thermal Management
Device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage.
Proper thermal management is important in designs operating at the HI speed data rate (100KBS) with high capacitive
loads and high data duty cycles.
Power dissipation may be estimated from Table 6 “Power Dissipation Table”. Device power dissipation (Pd) is indicated
for 100% data duty cycle with no word gap null times and should be adjusted for the appropriate data duty cycle (DC).
Pd(application) = DC * [Pd(table) - 145mW] + 145mW, where DC is the application data duty cycle, Pd(table) is the Pd
from the table for the indicated data rate and bus load, and 145mW is the quiescent power. The application’s data duty
cycle (DC) for 100KBS operation is calculated as:
DC = (total bits transmitted in 10 sec period / 1,000,000) =
(32 x total ARINC words transmitted in 10 sec period / 1,000,000).
Heat transfer from the IC package should be maximized. Use maximum trace width on all power and signal connections
at the IC. Place vias on the signal/power traces close to the IC to maximize heat flow to the internal power planes. If
possible, design a solid heat spreader land under and beyond the IC to maximize heat flow from the device.
©2008 Device Engineering Incorporated
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DS-MW-01022-01 Rev. C
7/21/09
Table 6: Power Dissipation Table
100% Duty Cycle, Full Load = 400Ω/30,000pF Half Load = 4,000Ω/10,000pF
Pd
LOAD
POWER
POWER
DATA RATE
LOAD
+V @ 15V
-V @ -15V V
1
, V
REF
@ 5V
0 to 100kbps
NONE
2.0mA
-5.0mA
4mA
125mW
0.0mW
12.5kbps
FULL
16.0mA
19.0mA
4mA
485mW
60.0mW
100kbps
FULL
48.0mA
51.0mA
4mA
1194mW
*
325.0mW
12.5kbps
HALF
6.0mA
8.0mW
4mA
196mW
30.0mW
100kbps
HALF
22.0mA
25.0mA
4mA
561mW
162.5mW
*
May require heat sink @ T
A
= +85
°C
Table 7: DC Electrical Characteristics
Conditions: Temperature: -55°C to +85°C, +V = +11.4VDC to +16.5VDC, –V = -11.4VDC to –16.5VDC; V
1
= V
REF
= +5VDC ±5%
SYMBOL
IQ+V
IQ-V
IQV
1
IQV
REF
V
IH
V
IL
I
IH
I
IL
I
OHSC
I
OLSC
V
OH
V
NULL
V
OL
I
CT
+
-
ISC (+V)
ISC (-V)
R
OUT
C
IN
PARAMETER
Quiescent +V
supply current
Quiescent -V
supply current
Quiescent V
1
supply current
Quiescent V
REF
supply
current
Logic 1 Input V
Logic 0 Input V
Logic 1 Input I
Logic 0 Input I
Output Short
Circuit Current (Output
High)
Output Short Circuit
Current (Output Low)
Output Voltage HIGH.
( +1)
Output Voltage NULL.
(0)
Output Voltage LOW.
( -1 )
Timing Capacitor
Charge Current
C
A
(+1 ) C
B
(-1 )
C
A
(-1 ) C
B
(+1 )
+V Short Circuit
Supply Current
-V Short Circuit
Supply Current
Resistance on
each output
Input Capacitor
MIN
-
-
-
-
2.0
-
-
-
-80
TYP
2
5
4
10
-
-
-
-
-
MAX
-
-
-
-
-
0.6
10
-20
-
UNIT
mA
mA
mA
µA
V
V
µA
µA
mA
TEST CONDITIONS
No Load. 429 mode.
DATA = CLOCK = SYNC = LOW
No Load. 429 mode.
DATA = CLOCK = SYNC = LOW
No Load. 429 mode.
DATA = CLOCK = SYNC = LOW
No Load. 429 mode.
DATA = CLOCK = SYNC = LOW
No Load.
No Load.
No Load.
No Load. (429/422´ Pin I
IL
= -2mA max)
Short to Ground
80
V
REF
-
250mV
-250
-V
REF
250mV
-
V
REF
-
-V
REF
-
V
REF
+
250mV
+250
-V
REF
+
250mV
mA
V
mV
V
Short to Ground
No Load. 429 Mode.
No Load. 429 Mode.
No Load. 429 Mode.
-
+200
–200
-
-
SeeNotes
-
-
µA
µA
mA
mA
pF
No Load. 429 Mode.
SYNC = CLOCK = HIGH
C
A
and C
B
held at zero volts.
-
-
-
-
+150
-150
-
15
Output short to ground
Output short to ground
Room Temp Only
-
Notes: For DEI1022 and DEI1023, the typical resistance on each output is 37.5
Ω.
For DEI1024 and DEI1025, the resistance on each output
is 0
Ω.
©2008 Device Engineering Incorporated
Page
4 of 10
DS-MW-01022-01 Rev. C
7/21/09
AC ELECTRICAL CHARACTERISTICS
Figure 3 shows the output waveform for the ARINC 429.
The output slew rates are controlled by timing capacitors C
A
and C
B
. They are charged by ±200µA (nom.).
Slew rate (SR) measured as V/µsec, is calculated by:
SR = 200/C
where C is in pF.
DATA(A)
DATA(B)
+V
REF
A
OUT
0V
-V
REF
+V
REF
B
OUT
0V
-V
REF
Figure 3: ARINC 429 Waveforms
Parameter
Output Rise Time
A
OUT
or B
OUT
C
A
= C
B
= 75pF
C
A
= C
B
= 500pF
Output Fall Time
A
OUT
or B
OUT
C
A
= C
B
= 75pF
C
A
= C
B
= 500pF
Symbol
Table 8: AC Electrical Characteristics
MIN MAX UNITS
NOTES
t
R
t
R
1.0
5.0
2.0
15.0
µsec
µsec
t
F
t
F
1.0
5.0
2.0
15.0
µsec
µsec
Input to Output
Propagation Delay
A
OUT
/ B
OUT
Skew Spec.
t
PNH
t
PNL
-
3.0
µsec
See Figure 4
-
-
500
nsec
©2008 Device Engineering Incorporated
Page
5 of 10
DS-MW-01022-01 Rev. C
7/21/09
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参数对比
与DEI1022-G相近的元器件有:DEI1024-G、DEI1024、DEI1025、DEI1025-G。描述及对比如下:
型号 DEI1022-G DEI1024-G DEI1024 DEI1025 DEI1025-G
描述 Line Driver, 2 Func, 2 Driver, BIPolar, PDSO14, GREEN, MS-012AB, SOIC-14 Line Driver, 2 Func, 2 Driver, BIPolar, PDSO14, GREEN, MS-012AB, SOIC-14 Line Driver, 2 Func, 2 Driver, BIPolar, PDSO14, MS-012AB, SOIC-14 Line Driver, 2 Func, 2 Driver, BIPolar, PDSO14, MS-012AB, SOIC-14 Line Driver, 2 Func, 2 Driver, BIPolar, PDSO14, GREEN, MS-012AB, SOIC-14
是否无铅 不含铅 不含铅 含铅 含铅 不含铅
是否Rohs认证 符合 符合 不符合 不符合 符合
零件包装代码 SOIC SOIC SOIC SOIC SOIC
包装说明 SOP, SOP, SOP, SOP, SOP,
针数 14 14 14 14 14
Reach Compliance Code compliant compliant compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99
差分输出 YES YES YES YES YES
驱动器位数 2 2 2 2 2
输入特性 STANDARD STANDARD STANDARD STANDARD STANDARD
接口集成电路类型 LINE DRIVER LINE DRIVER LINE DRIVER LINE DRIVER LINE DRIVER
接口标准 ARINC 429 ARINC 429 ARINC 429 ARINC 429 ARINC 429
JESD-30 代码 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609代码 e4 e4 e0 e0 e4
长度 8.636 mm 8.636 mm 8.636 mm 8.636 mm 8.636 mm
湿度敏感等级 1 1 2 2 1
标称负供电电压 -15 V -15 V -15 V -15 V -15 V
功能数量 2 2 2 2 2
端子数量 14 14 14 14 14
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SOP SOP SOP SOP SOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
峰值回流温度(摄氏度) 260 260 240 240 260
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.7526 mm 1.7526 mm 1.7526 mm 1.7526 mm 1.7526 mm
最大供电电压 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V
最小供电电压 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V
标称供电电压 5 V 5 V 5 V 5 V 5 V
电源电压1-最大 16.5 V 16.5 V 16.5 V 16.5 V 16.5 V
电源电压1-分钟 11.4 V 11.4 V 11.4 V 11.4 V 11.4 V
电源电压1-Nom 15 V 15 V 15 V 15 V 15 V
表面贴装 YES YES YES YES YES
技术 BIPOLAR BIPOLAR BIPOLAR BIPOLAR BIPOLAR
温度等级 OTHER OTHER OTHER OTHER OTHER
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 40 40 30 30 40
最大传输延迟 3000 ns 3000 ns 3000 ns 3000 ns 3000 ns
宽度 3.9116 mm 3.9116 mm 3.9116 mm 3.9116 mm 3.9116 mm
Base Number Matches 1 1 1 1 1
厂商名称 - Device Engineering Incorporated Device Engineering Incorporated Device Engineering Incorporated Device Engineering Incorporated
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