Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1044, DEI1045
QUAD ARINC 429
LINE RECEIVER
Features:
•
•
•
•
•
•
•
•
•
•
Converts ARINC 429 levels to TTL/CMOS digital data.
Meets requirements of ARINC 429 digital information transfer system standards.
Inputs internally protected to Lightning requirements of DO-160D level A3.
Operates at data rates beyond ARINC 429 specifications to 5MHz.
5 Volt or 3.3 Volt operation.
20L 4.4mm TSSOP Package.
One-half volt receiver hysteresis.
Operates within ±5 volts common mode input voltage range.
BiCMOS process
DEI1044 has TTL/CMOS test inputs
Functional Description:
The DEI1044 and DEI1045 are quad ARINC 429 Line Receiver ICs implemented in BICMOS technology. They contain four
differential line receivers. Each receiver channel translates incoming ARINC 429 data bus signals to a pair of TTL/CMOS outputs.
Each receiver operates independently, is lightning protected, and meets all requirements of the
ARINC 429 Digital Information
Transfer Standard.
The DEI1044 IC includes two TEST inputs for built in system test. They force the outputs of all receivers to the specified ZERO,
ONE or NULL state. The ARINC inputs are ignored when the device is in test mode. The DEI1045 does not have TEST inputs.
The DEI1044/1045 Quad Line Receiver can be used in conjunction with Device Engineering’s family of avionics products in
interfacing the ARINC 429 data bus.
IN
N
A
Table 1 Function Table
OUT
N
A
RESISTOR
NETWORK
AND
LIGHTNING
PROTECTION
IN
N
B
OUTPUT
AND
TEST
LOGIC
COMPARATORS
OUT
N
B
TEST
A
L
L
L
L
TEST
B
L
L
L
H
L
H
TESTA*
LIGHTNING
PROTECTION
TESTB*
IN
N
A -
IN
N
B
ONE
+10V
ZERO
-10V
NULL
0V
X
X
X
OUT
N
A
H
L
L
L
H
L
OUT
N
B
L
H
L
H
L
L
TO OTHER
CHANNELS
H
H
Notes:
1) One of four identical channels shown (N = 1 to 4)
2) * TEST inputs are No Connect on DEI1045
Test Inputs are internally set to L on DEI1045
Figure 1: Function Diagram
© 2010 Device Engineering Incorporated
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Pinout
IN1 A
IN1 B
IN2 A
1
20
OUT1 A
OUT1 B
OUT2 A
OUT2 B
V
DD
GND
OUT3 A
OUT3 B
OUT4 A
OUT4 B
2
19
3
18
Figure 2:
20L TSSOP Pinout
Note: * Pins 5 and 6 are “No Connect”
on DEI1045
IN2 B
TESTA *
TESTB *
IN3 A
IN3 B
IN4 A
IN4 B
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Electrical Characteristics
Table 2: Absolute Maximum Ratings
PARAMETER
Supply Voltage (VDD)
Storage Temperature
Input Voltage (ARINC Inputs) DC conditions.
Input Voltage (Test Inputs)
Power Dissipation @ 85 °C
MIN
-0.3
-65
-30
V
SS
– 0.3
MAX
7.0
+150
+30
V
CC
+0.3
350
260
UNITS
V
°C
V
V
mW
°C
V
V
Peak Body Temperature,
- G Package
Lightning Protection (ARINC 429 Channel Inputs and TESTA/TESTB Inputs)
Waveform 3
(2)
Waveform 4 and 5
(2)
NOTES:
-600
-300
+600
+300
1.
2.
3.
Stresses above these limits can cause permanent damage.
Per DO160D, Sect 22 Level 3A. See Figures 7-9.
The DEI1044 contains circuitry to protect inputs against damage due to high voltage static discharge. It has been
characterized per JEDEC A114-A Human Body Model to Level 1 (1KV io immunity). Observe precautions for
handling and storing Electrostatic Sensitive Devices.
Table 3: Recommended Operating Conditions
PARAMETER
Supply Voltage
Logic Input Levels (DEI1044)
Operating Temperature
-TMS
SYMBOL
VDD
V
TESTA,B
Top
CONDITIONS
+5V ± 10%
+3.3V ± 10%
0 to Vcc
-55 to +85°C
-55 to +125°C
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Table 4: Electrical Characteristics
Conditions: Temperature: -55°C to +85°C (std versions), -55°C to +125°C (-TMS versions)
V
DD
= +5V ± 10% or 3.3V ± 10%
PARAMETER
V
A
– V
B
V
A
– V
B
V
A
– V
B
Input Resistance
IN
A
to IN
B
Input Resistance
IN
A
or IN
B
to V
SS
Input Hysteresis
Input Capacitance
IN
A
to IN
B
Input Capacitance
IN
A
or IN
B
to V
SS
Input Common
Mode Voltage
Logic 0 Voltage
Logic 1 Voltage
Logic 0 Current
Logic 1 Current
OUT A or OUT B
OUT A or OUT B
OUT A or OUT B
OUT A or OUT B
V
IL
= 0.8
V
IH
= 2.0
V
DD
open,
C
IN
Shorted to V
SS
or +5V (1)
V
DD
open,
C
S
Shorted to V
SS
or +5V (1)
V
HI,
V
LO,
V
NULL
V
CM
at nominal values
TEST INPUTS (DEI1044 only)
V
IL
V
IH
I
IL
I
IH
2.4
0.4
V
DD
–
50mV
V
SS
+
50mV
5.5
11
2.0
1
20
TEST CONDITION
OUT A = 1
OUT B = 1
OUT A = 0
OUT B = 0
V
DD
open,
Shorted to V
SS
or +5V (1)
V
DD
open,
Shorted to V
SS
or +5V
SYMBOL
V
HI
V
LO
V
NULL
R
IN
R
S
MIN
6.5
-6.5
-2.5
24k
12k
0.5
1.0
50
50
-5
+5
0.8
NOM
10
-10
0
MAX
13
-13
2.5
UNITS
V
V
V
Ω
Ω
V
pF
pF
V
V
V
µA
µA
V
V
V
V
ARINC INPUTS
OUTPUTS
I
OH
= 5mA, V
dd
= 5V (1)
V
OH
I
OH
= 1.5mA, V
dd
= 3.3V
I
OL
= 5mA, V
dd
= 5V (1)
V
OL
I
OL
= 1.5mA, V
dd
= 3.3V
I
OH
= 100µA (1)
V
OH
CMOS Compatible
I
OL
= 100µA (1)
V
OL
CMOS Compatible
SUPPLY CURRENT
A/B IN open, A/B OUT open
I
DD
V
DD
Current
mA
SWITCHING CHARACTERISTICS (1)
Max 3.3V
Prop DelayIN A/B to OUT A/B
Prop DelayIN A/B to OUT A/B
OUT A/B rise time
TESTA = TESTB = 0
TESTA = TESTB = 0
10% to 90%
t
LH
t
HL
t
r
95
70
50
Max 5V
55
45
35
ns
ns
ns
OUT A/B fall time
10% to 90%
t
f
25
15
ns
TESTA/B to OUT A/B
t
TOH
90
50
ns
Prop delay
TESTA/B to OUT A/B
t
TOL
90
50
ns
Prop delay
Notes
1. Guaranteed by design, not production tested.
2.
Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect
to Ground unless otherwise noted.
© 2010 Device Engineering Incorporated
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V/I
IN A
V
A
- V
B
=
6.5V
V
A
- V
B
=
-6.5V
Largest
Peak
25% to 75%
of Largest Peak
50%
IN B
t
LH
t
HL
1.5V
0
t
OUT A
OUT B
t
LH
t
HL
Figure 7: DO160C/D Voltage Waveform #3
1.5V
V
OC
= 600V, I
SC
= 24A, Frequency = 1.0MHZ ±20%
V
Peak
Figure 3: Input/Output Timing
TESTA OR B
1.5V
t
TOH
50%
T1 = 6.4 microseconds ±20%
T2 = 70 microseconds ±20%
t
TOL
OUTA OR B
1.5V
0
T1
T2
t
Figure 8: DO160C/D Voltage Waveform #4
Figure 4: TEST Propagation Delay
V/I
Peak
V
OC
= 300V, I
SC
= 60A
5A:
T1 = 40 microseconds ±20%
T2 = 120 microseconds ±20%
T2 = 500 microseconds ±20%
5B:
T1 = 50 microseconds ±20%
OUTA or OUTB
50pF
50%
Figure 5: Output Load
0
T1
T2
t
Figure 9: DO160C/D Voltage Waveform #5
V
OC
= 300V, I
SC
= 300A
t
r
OUTA or B
90%
t
f
10%
Figure 6: Rise/Fall Time
Notes:
1. V
OC
= Peak Open Circuit Voltage
available at the calibration point.
2. I
SC
= Peak Short Circuit Current available
at the calibration point.
3. Amplitude tolerances: +10%, -0%
4. The ratio of V
OC
to I
SC
is the generator
source impedance to be used for
generator calibration purposes.
© 2010 Device Engineering Incorporated
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Package Description:
Figure 10: 20L TSSOP Package Dimensions
© 2010 Device Engineering Incorporated
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