www.maxim-ic.com
DS1244/DS1244P
256k NV SRAM
with Phantom Clock
PIN ASSIGNMENT (Top View)
A14/RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
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FEATURES
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§
§
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Real-time clock (RTC) keeps track of
hundredths of seconds, minutes, hours, days,
date of the month, months, and years
32k x 8 NV SRAM directly replaces volatile
static RAM or EEPROM
Embedded lithium energy cell maintains
calendar operation and retains RAM data
Watch function is transparent to RAM
operation
Month and year determine the number of
days in each month; valid up to 2100
Full 10% operating range
Operating temperature range: 0°C to +70°C
Over 10 years of data retention in the
absence of power
Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
DIP module only
Standard 28-pin JEDEC pinout
PowerCap
®
module board only
– Surface mountable package for direct
connection to PowerCap containing
battery and crystal
– Replaceable battery (PowerCap)
– Pin-for-pin compatible with DS1248P
and DS1251P
Underwriters Laboratory (UL) recognized
DS2144
28-PDIP Module (740mil)
RST
N.C.
N.C.
N.C.
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
§
DS1244P
34-Pin PowerCap Module
(Uses DS9034PCX PowerCap)
Package Dimension Information
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
PowerCap is a registered trademark of Dallas Semiconductor.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
http://www.maxim-ic.com/errata.
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081902
DS1244/DS1244P
PIN DESCRIPTION
A
0
–A
14
CE
OE
WE
TYPICAL OPERATING CIRCUIT
V
CC
GND
DQ
0
–DQ
7
N.C.
X1, X2
V
BAT
RST
- Address Inputs
- Chip Enable
- Output Enable
- Write Enable
- Power-Supply Input
- Ground
- Data In/Data Out
- No Connection
- Crystal Connection
- Battery Connection
- Reset
ORDERING INFORMATION
PART
DS1244Y-70
DS1244YP-70
DS1244W-120
DS1244W-120IND
DS1244WP-120
DS1244WP-120IND
PIN-PACKAGE
28-Module (740mil)
34-PowerCap
*
28-Module (740mil)
28-Module (740mil)
34-PowerCap
*
34-PowerCap
*
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
TOP MARK
DS1244Y-70
DS1244YP-70
DS1244W-120
DS1244W-120IND
DS1244WP-120
DS1244WP-120IND
*
DS9034PCX (PowerCap) Required.
(Must be ordered separately.)
DESCRIPTION
The DS1244 256k NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32k words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors V
CC
for an out-of-tolerance
condition. When such a condition occurs, the lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.
The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
PACKAGES
The DS1244 is available in two packages: 28-pin DIP and 34-pin PowerCap module. The 28-pin DIP-
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1244P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the Powercap is
DS9034PCX.
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DS1244/DS1244P
RAM READ MODE
The DS1244 executes a read cycle whenever
WE (write enable) is inactive (high) and CE (chip enable)
is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within t
ACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable)
access times and states are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t
CO
for
CE or t
OE
for OE , rather than address access.
RAM WRITE MODE
The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (t
WR
) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE
active) then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power fail point, V
PF
(point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point, V
SO
(battery supply level), device power is switched from the V
CC
pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V
CC
is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when V
CC
is greater than V
PF
.
When V
CC
fall as below the V
PF
, access to the device is inhibited. If V
PF
is less than V
BAT
, the device
power is switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops below V
PF
. If V
PF
is greater
than V
BAT
, the device power is switched from V
CC
to the backup supply (V
BAT
) when V
CC
drops below
V
BAT
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to nominal
levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using
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DS1244/DS1244P
the
CE
and
OE
control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CE
and
WE
control of the SmartWatch. These 64 write cycles are used only to gain access to the
phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the
OE
pin or the
WE
pin. Cycles to other
locations outside the memory block can be interleaved with
CE
cycles without interrupting the pattern
recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
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DS1244/DS1244P
Figure 1. PHANTOM CLOCK REGISTER DEFINITION
Note:
The pattern recognition in hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 10
19
. This
pattern is sent to the phantom clock LSB to MSB.
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