DS2164Q
G.726 ADPCM Processor
www.maxim-ic.com
FEATURES
§
§
Compresses/expands 64kbps PCM voice
to/from either 32kbps, 24kbps, or 16kbps
Dual fully independent channel architecture;
device can be programmed to perform either:
-
two expansions
-
two compressions
-
one expansion and one compression
Interconnects directly to combo-codec
devices
Input to output delay is less than 375ms
Simple serial port used to configure the
device
On-board time-slot assigner-circuit (TSAC)
function allows data to be input/output at
various time slots
Supports Channel Associated Signaling
Each channel can be independently idled or
placed into bypass
Available hardware mode requires no host
processor; ideal for voice storage
applications
Backward-compatible with the DS2165Q
ADPCM processor chip
Single +5V supply; low-power CMOS
technology
Available in 28-pin PLCC
PIN ASSIGNMENT (Top View)
TM1
TM0
RST
NC
VDD
YIN
CLKY
NC
A0
A1
A2
A3
A4
A5
5
6
7
8
9
10
11
12
13 14
15
16
17
18
4
3
2
1
28
27
26
25
24
23
DS2164Q
22
21
20
19
§
§
§
§
§
§
§
§
§
§
FSY
YOUT
CS
SDI
SCLK
XOUT
NC
DESCRIPTION
The DS2164Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been
optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three
different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from)
either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT
Recommendation G.726. The DS2164Q can switch compression algorithms on-the-fly. This allows the
user to make maximum use of the available bandwidth on a dynamic basis.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device errata,
click here:
http://www.maxim-ic.com/errata.
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070802
SPS
MCLK
VSS
NC
XIN
CLKX
FSX
28-Pin PLCC
DS2164Q
OVERVIEW
The DS2164Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two
independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM)
backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz
master clock is required by the DSP engine. The DS2164Q can be configured to perform either two
expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces
support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for
m-law
and
2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream
during a user-programmed input time slot, processes the data and outputs the result during a user-
programmed output time slot.
Each PCM interface has a control register that specifies functional characteristics (compress, expand,
bypass, and idle), data format (m-law or A-law), and algorithm reset control. With the SPS pin strapped
high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a
novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying
system-level interconnect.
With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control
register bits to some of the address and serial port pins. Under the hardware mode, no external host
controller is required and all PCM/ADPCM input and output time slots default to time slot 0.
HARDWARE RESET
RST
allows the user to reset both channel algorithms and the contents of the internal registers. This pin
must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the
device has initialized properly.
RST
should also be asserted when changing to or from the hardware
mode.
RST
clears all bits of the control register for both channels except the IPD bits; the IPD bits for
both channels are set to 1.
SOFTWARE MODE
Connecting SPS high enables the software mode. In this mode, an external host controller writes
configuration data to the DS2164Q by the serial port through inputs SCLK, SDI, and
CS
(Figure 2). Each
write to the DS2164Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the
address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X
or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1
byte to set the input time slot and another byte to set the output time slot.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the first byte written to the serial port; it identifies
which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must
match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If
an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.
Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs
are tri-stated during register updates.
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DS2164Q
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format, and channel coding for the
selected channel.
The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When
IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port
must not be operated faster than 39kHz.
ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared
by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PIN
2
3
4
6
7
8
9
10
11
12
13
14
16
17
18
20
21
22
23
24
25
26
27
28
SYMBOL
RST
TYPE
I
I
FUNCTION
Reset.
A high-low-high transition resets the algorithm. The device should be
reset on power-up and when changing to or from the hardware mode.
Test Modes 0 and 1.
Connect to V
SS
for normal operation.
TM0
TM1
A0
A1
A2
A3
A4
A5
SPS
MCLK
VSS
XIN
CLKX
FSX
XOUT
SCLK
SDI
CS
I
Address Select.
A0 = LSB, A5 = MSB. Must match address/command word
to enable the serial port.
I
I
—
I
I
I
O
I
I
I
O
I
I
I
—
Serial Port Select.
Connect to V
DD
to select the serial port; connect to V
SS
to
select the hardware mode.
Master Clock.
10MHz clock for the ADPCM processing engine; may be
asynchronous to SCLK, CLKX, and CLKY.
Signal Ground.
0V
X Data In.
Sampled on falling edge of CLKX during selected time slots.
X Data Clock.
Data clock for the X-side PCM interface; must be
synchronous with FSX.
X Frame Sync.
8kHz frame sync for the X-side PCM interface.
X Data Output.
Updated on rising edge of CLKX during selected time slots.
Serial Data Clock.
Used to write to the serial port registers.
Serial Data In.
Data for on-board control registers; sampled on the rising
edge of SCLK. LSB sent first.
Chip Select.
Must be low to write to the serial port.
Y Data Output.
Updated on rising edge of CLKY during selected time slots.
Y Frame Sync.
8kHz frame sync for the Y-side PCM interface.
Y Data Clock.
Data clock for the Y-side PCM interface; must be
synchronous with FSY.
Y Data In.
Sampled on falling edge of CLKY during selected time slots.
Positive Supply.
5.0V
YOUT
FSY
CLKY
YIN
VDD
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DS2164Q
Figure 1. BLOCK DIAGRAM
Figure 2. SERIAL PORT WRITE
Note:
A 2-byte write is shown.
The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or
compression occurs. Bypass operates on bytewide (8 bits) slots when CP/
EX
is set and on nibble-wide
(4 bits) slots when CP/
EX
is cleared.
A-law (U/
A
= 0) and
m-law
(U/
A
= 1) PCM coding is independently selected for the X and Y channels
by CR.2. If BYP and IPD are cleared, then CP/
EX
determines if the input data is to be compressed or
expanded.
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DS2164Q
Figure 3. ADDRESS/COMMAND BYTE
(MSB)
—
SYMBOL
—
X/
Y
A5
A4
A3
A2
A1
A0
X/
Y
POSITION
ACB.7
ACB.6
ACB.5
ACB.4
ACB.3
ACB.2
ACB.1
ACB.0
A5
A4
A3
FUNCTION
Reserved. Must be 0 for proper operation
X/Y Channel Select
0 = update channel Y characteristics
1 = update channel X characteristics
MSB of device address
—
—
—
—
LSB of device address
A2
A1
(LSB)
A0
Figure 4. CONTROL REGISTER
(MSB)
AS0
SYMBOL
AS0
AS1
IPD
ALRST
BYP
(LSB)
AS1
POSITION
CR.7
CR.6
CR.5
CR.4
CR.3
CR.2
CR.1
CR.0
IPD
ALRST
BYP
FUNCTION
Algorithm Select 0 (Table 2)
Algorithm Select 1 (Table 2)
Idle and Power-Down
0 = channel enabled
1 = channel disabled (output tri-stated)
Algorithm Reset
0 = normal operation
1 = reset algorithm for selected channel
Bypass
0 = normal operation
1 = bypass selected channel
Data Format
0 = A-law
1 =
m-law
Algorithm Select 2 (Table 2)
Channel Coding
0 = expand (decode) selected channel
1 = compress (encode) selected channel
U/ A
AS2
CP/ EX
U/ A
AS2
CP/ EX
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