DS2187
Receive Line Interface
www.dalsemi.com
FEATURES
Line interface for T1 (1.544 MHz) and CEPT
(2.048 MHz) primary rate networks
Extracts clock and data from twisted pair or
coax
Meets requirements of PUB 43801, TR
62411, and applicable CCITT G.823
Precision on-chip PLL eliminates external
crystal or LC tank - no tuning required
Decodes AMI, B8ZS, and HDB3 coded
signals
Designed for short loop applications such as
terminal equipment to DSX-1
Reports alarm and error events
Compatible with the DS2180A T1/ISDN
Primary Rate and DS2181A CEPT
Transceivers, as well as DS2141A T1 and
DS2143 E1 Controllers
Companion to the DS2186 T1/CEPT
Transmit Line Interface and DS2188
T1/CEPT Jitter Attenuator
Single 5V supply; low-power CMOS
technology
PIN ASSIGNMENT
AVDD
RAIS
ZCSEN
NC
LCAP
RCLKSEL
RTIP
RRING
LOCK
AVSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DVDD
RCL
AIS
BPV
NC
NC
RPOS
RNEG
RCLK
DVSS
20-Pin SOIC (300-mil)
AVDD
RAIS
ZCSEN
LCAP
RCLKSEL
RTIP
RRING
LOCK
AVSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
DVDD
RCL
AIS
BPV
NC
RPOS
RNEG
RCLK
DVSS
18-Pin DIP (300-mil)
DESCRIPTION
The DS2187 T1/CEPT Receive Line Interface chip interfaces user equipment to North American (T1
1.544 MHz) and European (CEPT 2.048 MHz) primary rate communication networks. The device
extracts clock and data from twisted pair or coax transmission media and eliminates expensive discrete
components and/or manual tuning required in existing T1 and CEPT line termination electronics.
Application areas include DACS, CSU, CPE, channel banks, and PABX-to-computer interfaces such as
DMI and CPI.
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062101
DS2187
DS2187 BLOCK DIAGRAM
Figure 1
LINE INPUT
Input signals are coupled to the DS2187 via a 1:2 center-tapped transformer as shown in Figure 2. For T1
applications, R1 and R2 must be 200 ohms in order to properly terminate the line at 100 ohms. R1 and R2
are set at 150 or 240 ohms for CEPT applications. Special internal circuitry of the RTIP and RRING
inputs permits negative signal excursions below V
SS
, which will occur in the circuit in Figure 2.
PEAK DETECTOR AND SLICERS
Signal pulses present at RTIP and RRING are sampled by an internal peak detect circuit. The clock and
data slicer threshold are set for 50% of the sampled peak voltage.
Peak input levels at RRIP and RRING must exceed 0.6 volts to establish minimum slicer thresholds.
Signals below this level will cause RCL to transition high after 192 bit times.
CLOCK EXTRACTION
The DS2187 utilizes both frequency locked (FLL) and digital phase locked (DPLL) loops to recover data
and clock from the incoming AMI signal. T1 applications utilize a 18.528 MHz clock divided by either
11, 12, or 13 to match the phase of the incoming jittered line signal. This technique affords exceptional
jitter tracking which enables the DS2187 to meet the latest AT&T TR 62411 and ECSA jitter
specifications. A 24.576 MHz clock divided by 11, 12, or 13 provides jitter tracking in the CEPT mode.
The DPLL output is buffered and presented at RCLK. An on-chip, laser-trimmed, voltage-controlled
oscillator (V
CO
) provides the precision 18.528 MHz and 24.576 MHz frequency sources utilized in the
FLL. The FLL is a high-Q circuit which tracks the average frequency of the incoming signal, minimizing
the effect of the DPLL on output jitter.
During the acquisition time or if RCL goes high, the LOCK pin will go low to indicate a loss of
synchronization to the line signal. Once this pin goes high, the FLL has achieved frequency lock and
valid data is present at the RPOS and RNEG outputs.
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DS2187
PIN DESCRIPTION
Table 1
PIN
1
2
SYMBOL
AVDD
TYPE
-
I
DESCRIPTION
Analog Positive Supply.
5.0 volts.
Reset Alarm Indication Signal.
Every other low pulse at this input
establishes the AIS alarm detection period.
0 Code Suppression Enable.
When high, incoming B8ZS (RCLKSEL=0)
or HDB3 (RCLKSEL=1) code words are replaced with all 0s at RPOS and
RNEG; when low, no code replacement occurs.
Loop Cap.
Part of internal loop filter; attach a 10 microfarad capacitor from
this pin to V
SS
.
Receive Clock Select.
Tie to V
SS
for 1.544 MHz (T1) applications, to V
DD
for
2.048 MHz (CEPT) applications.
Receive Tip and Ring.
Connect to line transformer as shown in Figure 2.
Frequency Lock.
High state indicates that internal circuitry is phase- and
frequency-locked to the incoming signal at RRING and RTIP.
Analog Signal Ground.
0.0 volts.
Digital Signal Ground.
0.0 volts.
Receive Clock.
Extracted line rate clock.
Receive Data.
Extracted receive data; updated on rising edge of RCLK.
No Connect.
Do not connect to this pin.
Bipolar Violation.
Transitions high for the full bit period when a bit in
violation appears at RPOS or RNEG; B8ZS code words are not accused when
ZCSEN=1. BPV not valid for RCLKSEL=1 and ZCSEN=1.
Alarm Indication Signal.
High when the received data stream has contained
RAIS
ZCSEN
3
I
4
5
6
7
8
9
10
11
12
13
14
15
LCAP
RCLKSEL
RTIP
RRING
LOCK
AVSS
DVSS
RCLK
RNEG
RPOS
NC
BPV
-
I
I
O
-
-
O
O
-
O
16
17
18
AIS
RCL
DVDD
O
O
-
less than three 0s during the last two periods of the RAIS signal.
Receive Carrier Loss.
High if 192 0s appear at RPOS and RNEG; reset on
next occurrence of a one.
Digital Positive Supply.
5.0 volts
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DS2187
SYSTEM LEVEL INTERCONNECT
Figure 2
OUTPUT TIMING
Figure 3
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DS2187
0 CODE SUPPRESSION
The device will decode incoming B8ZS (RCLKSEL=0) or HDB3 (RCLKSEL=1) code words and replace
them with an all-0 code when ZCSEN=1. When ZCSEN=0, code words will pass through the device
without being altered. This feature can be disabled when the DS2187 is used with transceiver devices
such as the DS2180A DS2181A, DS2141A, or DS2143.
ALARM DETECTION
The extracted data is monitored for network alarm and error conditions. RCL is set when 192 consecutive
0s occur; it is cleared on the next one occurrence. AIS is set when less than three 0s have appeared at
RPOS and RNEG during the last two periods of the
RAIS
signal; once set, AIS will remain high for the
next two periods of
RAIS
. AIS will return low when more than two 0s appear. BPV reports bipolar
violations as they occur at RPOS and RNEG; B8ZS code words will not be flagged by BPV when
ZCSEN=1.
BYPASSING AND
LAYOUT CONSIDERATIONS
The DS2187 contains both precision analog and high-speed digital circuitry on the same chip. The power
supplies of these circuits (AVDD, AVSS, DVDD and DVSS) should be connected to system analog and
digital supplies. If separate system supplies do not exist, the appropriate supply pins can be tied together.
Tying the analog and digital supplies together on the DS2187 will not degrade its performance, provided
the power supply is sufficiently decoupled.
To assure optimum performance, the length of LCAP, RTIP and RRING printed circuit board traces
should be minimized and isolated from neighboring interconnect.
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