DS3181/DS3182/DS3183/DS3184
Single/Dual/Triple/Quad
ATM/Packet PHYs with Built-In LIU
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3181, DS3182, DS3183, and DS3184
(DS318x)
integrate ATM
cell/HDLC
packet
processor(s) with a DS3/E3 framer(s) and LIU(s) to
map/demap ATM cells or packets into as many as
four DS3/E3 physical copper lines with DS3-framed,
E3-framed, or clear-channel data streams on per-port
basis.
FUNCTIONAL DIAGRAM
DS3/E3/STS-1 LIU
DS3/E3/STS-1
PORTS
APPLICATIONS
Access Concentrators
SONET/SDH ADM
SONET/SDH Muxes
PBXs
Digital Cross Connect
Test Equipment
Routers and Switches
Integrated Access
Device (IAD)
Multiservice Access
Platform (MSAP)
Multiservice Protocol
Platform (MSPP)
ATM and Frame Relay
Equipment
PDH Multiplexer/
Demultiplexer
CELL/
DS3/E3
PACKET
FRAMER/
FORMATTER PROCESSOR
SYSTEM
INTERFACE
POS-PHY
OR
UTOPIA
DS318x
FEATURES
Single (DS3181), Dual (DS3182), Triple
(DS3183), or Quad (DS3184) with Integrated LIU
ATM/Packet PHYs for DS3, E3, and Clear-
Channel 52Mbps (CC52)
Pin Compatible for Ease of Port Density
Migration in the Same PC Board Platform
Each Port Independently Configurable
Perform Receive Clock/Data Recovery and
Transmit Waveshaping
Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
Interfaces to 75Ω Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3) or 440 Meters or
1443 Feet (E3)
Uses 1:2 Transformers on Both Tx and Rx
Universal PHYs Map ATM Cells and/or HDLC
Packets into DS3 or E3 Data Streams
UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3
Interface with 8-, 16-, or 32-Bit Bus Width
66MHz UTOPIA L3 and POS-PHY L3 Clock
52MHz UTOPIA L2 and POS-PHY L2 Clock
Ports Independently Configurable for Cell or
Packet Traffic in POS-PHY Bus Modes
Direct, PLCP, DSS, and Clear-Channel Cell
Mapping
ORDERING INFORMATION
PART
DS3181
DS3181N
DS3182
DS3182N
DS3183
DS3183N
DS3184
DS3184N
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
Note:
Add the “+” suffix for the lead-free package option.
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1
REV: 102406
DS3181/DS3182/DS3183/DS3184
FEATURES (continued)
Direct and Clear-Channel Packet Mapping
On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s)
Ports Independently Configurable for DS3, E3
(Full or Subrate) or Arbitrary Framing Protocols
Up to 52Mbps
Programmable (Externally Controlled or
Internally Finite State Machine Controlled)
Subrate DS3/E3
Full-Featured DS3/E3/PLCP Alarm Generation
and Detection
Built-In HDLC Controllers with 256-Byte FIFOs
for Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes and PLCP NR/GC
Bytes
On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis
Large Performance-Monitoring Counters for
Accumulation Intervals of at Least 1 Second
Flexible Overhead Insertion/Extraction Ports for
DS3, E3, and PLCP Framers
Loopbacks Include Line, Diagnostic, Framer,
Payload, Analog, and System Interface with
Capabilities to Insert AIS in the Directions Away
from Loopback Directions
Ports can be Disabled to Reduce Power
Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz
(DS3), 34.368MHz (E3), and 52MHz (Arbitrary
Framing at Up to 52Mbps) from a Single Clock
Reference Source at One of Those Three
Frequencies
Pin Compatible with the DS3171/2/3/4 Family
and the DS3161/2/3/4 Family
8/16-Bit Generic Microprocessor Interface
Low-Power (2.7W typ) 3.3V Operation (5V-
Tolerant I/O)
Small, High-Density, Thermally Enhanced, BGA
Packaging (TE-PBGA) with 1.27mm Pin Pitch
Industrial Temperature Operation:
-40°C to +85°C
IEEE1149.1 JTAG Test Port
DETAILED DESCRIPTION
The DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs perform all the functions
necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3
(34.368Mbps) framed, or 52Mbps clear-channel data streams on DS3, E3, or STS-1 physical copper lines. Each
line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and
data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal or can be
bypassed for direct clock and data inputs. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The
transmitter LIU drives standard pulse-shape waveforms onto 75Ω coaxial cable or can be bypassed for direct clock
and data outputs. The jitter attenuator can be placed in either transmit or receive data path when the LIU is
enabled. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission
and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in
properly formatted M23 DS3, C-bit DS3, G.751 E3, or G.832 E3 data streams. PLCP framers provide legacy ATM
transmission-convergence support. DSS scrambling is performed for clear-channel ATM cell support. With
integrated hardware support for both cells and packets, the DS318x DS3/E3 ATM/Packet PHYs provide system on-
chip solutions (from DS3/E3/STS-1 physical copper lines to ATM/Packet UTOPIA/POS-PHY Level 2/3 system
switch) for universal high-density line cards in the unchannelized DS3/E3/clear-channel DS3 ATM/Packet
applications. Unused functions can be powered down to reduce device power. The DS318x ATM/Packet PHYs with
embedded LIU conform to the telecommunications standards listed in Section
4.
2
DS3181/DS3182/DS3183/DS3184
TABLE OF CONTENTS
1
2
3
BLOCK DIAGRAMS
APPLICATIONS
FEATURE DETAILS
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
14
15
17
G
LOBAL
F
EATURES
.......................................................................................................................17
R
ECEIVE
DS3/E3/STS-1 LIU F
EATURES
.......................................................................................17
R
ECEIVE
DS3/E3 F
RAMER
F
EATURES
...........................................................................................17
R
ECEIVE
PLCP F
RAMER
F
EATURES
..............................................................................................18
R
ECEIVE
C
ELL
P
ROCESSOR
F
EATURES
.........................................................................................18
R
ECEIVE
P
ACKET
P
ROCESSOR
F
EATURES
.....................................................................................18
R
ECEIVE
FIFO F
EATURES
.............................................................................................................19
R
ECEIVE
S
YSTEM
I
NTERFACE
F
EATURES
.......................................................................................19
T
RANSMIT
S
YSTEM
I
NTERFACE
F
EATURES
.....................................................................................19
T
RANSMIT
FIFO F
EATURES
...........................................................................................................19
T
RANSMIT
C
ELL
P
ROCESSOR
F
EATURES
.......................................................................................19
T
RANSMIT
P
ACKET
P
ROCESSOR
F
EATURES
...................................................................................19
T
RANSMIT
PLCP F
ORMATTER
F
EATURES
......................................................................................20
T
RANSMIT
DS3/E3 F
ORMATTER
F
EATURES
...................................................................................20
T
RANSMIT
DS3/E3/STS-1 LIU F
EATURES
.....................................................................................20
J
ITTER
A
TTENUATOR
F
EATURES
....................................................................................................20
C
LOCK
R
ATE
A
DAPTER
F
EATURES
.................................................................................................20
HDLC O
VERHEAD
C
ONTROLLER
F
EATURES
..................................................................................20
FEAC C
ONTROLLER
F
EATURES
....................................................................................................21
T
RAIL
T
RACE
B
UFFER
F
EATURES
...................................................................................................21
B
IT
E
RROR
R
ATE
T
ESTER
(BERT) F
EATURES
................................................................................21
L
OOPBACK
F
EATURES
...................................................................................................................21
M
ICROPROCESSOR
I
NTERFACE
F
EATURES
.....................................................................................21
S
UBRATE
F
EATURES
(F
RACTIONAL
DS3/E3)..................................................................................21
T
EST
F
EATURES
............................................................................................................................22
4
5
6
STANDARDS COMPLIANCE
ACRONYMS AND GLOSSARY
MAJOR OPERATIONAL MODES
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
23
25
26
DS3/E3 ATM/P
ACKET
M
ODE
........................................................................................................26
DS3/E3 ATM/P
ACKET
—OHM M
ODE
............................................................................................27
DS3/E3 I
NTERNAL
F
RACTIONAL
(S
UBRATE
) ATM/P
ACKET
M
ODE
...................................................28
DS3/E3 E
XTERNAL
F
RACTIONAL
(S
UBRATE
) ATM/P
ACKET
M
ODE
..................................................29
DS3/E3 F
LEXIBLE
E
XTERNAL
F
RACTIONAL
(S
UBRATE
) M
ODE
C
ONFIGURATION
M
ODE
....................30
DS3/E3 G.751 PLCP ATM M
ODE
................................................................................................31
DS3/E3 G.751 PLCP ATM—OHM M
ODE
....................................................................................32
C
LEAR
-C
HANNEL
ATM/P
ACKET
M
ODE
...........................................................................................34
C
LEAR
-C
HANNEL
ATM/P
ACKET
—OHM M
ODE
..............................................................................35
C
LEAR
-C
HANNEL
O
CTET
A
LIGNED
ATM/P
ACKET
—OHM M
ODE
.....................................................36
7
MAJOR LINE INTERFACE OPERATING MODES
7.1
7.2
7.3
7.4
37
DS3HDB3/B3ZS/AMI LIU M
ODE
.................................................................................................37
HDB3/B3ZS/AMI N
ON
-LIU L
INE
I
NTERFACE
M
ODE
.......................................................................39
UNI L
INE
I
NTERFACE
M
ODE
..........................................................................................................40
UNI L
INE
I
NTERFACE
—OHM M
ODE
..............................................................................................41
8
PIN DESCRIPTIONS
3
42
DS3181/DS3182/DS3183/DS3184
8.1
8.2
8.3
S
HORT
P
IN
D
ESCRIPTIONS
............................................................................................................42
D
ETAILED
P
IN
D
ESCRIPTIONS
........................................................................................................48
P
IN
F
UNCTIONAL
T
IMING
................................................................................................................66
Line IO.................................................................................................................................................. 66
DS3/E3 Framing and PLCP Overhead Functional Timing................................................................... 69
Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing ................. 72
Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing ....................................... 73
UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing........................................................... 75
Microprocessor Interface Functional Timing ........................................................................................ 87
JTAG Functional Timing....................................................................................................................... 91
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
9
INITIALIZATION AND CONFIGURATION
9.1
9.1.1
9.1.2
9.1.3
92
M
ONITORING AND
D
EBUGGING
......................................................................................................94
Cell/Packet FIFO.................................................................................................................................. 94
Cell Processor...................................................................................................................................... 94
Packet Processor ................................................................................................................................. 95
10 FUNCTIONAL DESCRIPTION
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.1.7
10.1.8
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
96
10.1 P
ROCESSOR
B
US
I
NTERFACE
........................................................................................................96
8/16-Bit Bus Widths.............................................................................................................................. 96
Ready Signal (
RDY
) ............................................................................................................................. 96
Byte Swap Modes ................................................................................................................................ 96
Read-Write/Data Strobe Modes........................................................................................................... 96
Clear on Read/Clear on Write Modes .................................................................................................. 96
Global Write Method ............................................................................................................................ 97
Interrupt and Pin Modes....................................................................................................................... 97
Interrupt Structure ................................................................................................................................ 97
Line Clock Modes................................................................................................................................. 99
Sources of Clock Output Pin Signals ................................................................................................. 100
Line IO Pin Timing Source Selection ................................................................................................. 103
Clock Structures On Signal IO Pins ................................................................................................... 105
Gapped Clocks................................................................................................................................... 106
10.2 C
LOCKS
........................................................................................................................................99
10.3 R
ESET AND
P
OWER
-D
OWN
..........................................................................................................107
10.4 G
LOBAL
R
ESOURCES
..................................................................................................................109
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
Clock Rate Adapter (CLAD)............................................................................................................... 109
8 kHz Reference Generation ............................................................................................................. 111
One-Second Reference Generation .................................................................................................. 113
General-Purpose IO Pins ................................................................................................................... 113
Performance Monitor Counter Update Details ................................................................................... 114
Transmit Manual Error Insertion ........................................................................................................ 115
10.5 P
ER
-P
ORT
R
ESOURCES
..............................................................................................................116
10.5.1 Loopbacks.......................................................................................................................................... 116
10.5.2 Loss Of Signal Propagation ............................................................................................................... 118
10.5.3 AIS Logic............................................................................................................................................ 118
10.5.4 Loop Timing Mode ............................................................................................................................. 121
10.5.5 HDLC Overhead Controller ................................................................................................................ 121
10.5.6 Trail Trace .......................................................................................................................................... 121
10.5.7 BERT.................................................................................................................................................. 121
10.5.8 Fractional Payload Controller............................................................................................................. 122
10.5.9 PLCP/Fractional port pins .................................................................................................................. 122
10.5.10 Framing Modes .................................................................................................................................. 127
10.5.11 Mapping Modes.................................................................................................................................. 128
10.5.12 Line Interface Modes.......................................................................................................................... 132
10.6 UTOPIA/POS-PHY/SPI-3 S
YSTEM
I
NTERFACE
...........................................................................134
10.6.1 General Description ........................................................................................................................... 134
10.6.2 Features ............................................................................................................................................. 134
10.6.6 System Interface Bus Controller ........................................................................................................ 135
4
DS3181/DS3182/DS3183/DS3184
10.7 ATM C
ELL
/HDLC P
ACKET
P
ROCESSING
.....................................................................................139
10.7.1
10.7.2
10.7.3
10.7.4
10.7.5
10.7.6
10.7.7
10.7.8
10.8.1
10.8.2
10.8.3
10.8.4
10.8.5
10.8.6
10.8.7
10.8.8
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
General Description ........................................................................................................................... 139
Features ............................................................................................................................................. 139
Transmit Cell/Packet Processor......................................................................................................... 140
Receive Cell/Packet Processor.......................................................................................................... 141
Cell Processor.................................................................................................................................... 141
Packet Processor ............................................................................................................................... 146
FIFO ................................................................................................................................................... 148
System Loopback............................................................................................................................... 149
General Description ........................................................................................................................... 150
Features ............................................................................................................................................. 150
Transmit PLCP Frame Processor ...................................................................................................... 151
Receive PLCP Frame Processor ....................................................................................................... 151
Transmit DS3 PLCP Frame Processor .............................................................................................. 151
Receive DS3 PLCP Frame Processor ............................................................................................... 154
Transmit E3 PLCP Frame Processor................................................................................................. 155
Receive E3 PLCP Frame Processor.................................................................................................. 158
General Description ........................................................................................................................... 160
Features ............................................................................................................................................. 160
Transmit Fractional Interface ............................................................................................................. 161
Transmit Fractional Controller............................................................................................................ 161
Receive Fractional Interface .............................................................................................................. 161
Receive Fractional Controller............................................................................................................. 161
10.8 DS3/E3 PLCP F
RAMER
..............................................................................................................150
10.9 F
RACTIONAL
P
AYLOAD
C
ONTROLLER
...........................................................................................160
10.10 DS3/E3 F
RAMER
/F
ORMATTER
....................................................................................................163
10.10.1 General Description ........................................................................................................................... 163
10.10.2 Features ............................................................................................................................................. 163
10.10.3 Transmit Formatter............................................................................................................................. 164
10.10.4 Receive Framer.................................................................................................................................. 164
10.10.5 C-bit DS3 Framer/Formatter .............................................................................................................. 168
10.10.6 M23 DS3 Framer/Formatter ............................................................................................................... 171
10.10.7 G.751 E3 Framer/Formatter............................................................................................................... 174
10.10.8 G.832 E3 Framer/Formatter............................................................................................................... 176
10.10.9 Clear-Channel Frame Processor ....................................................................................................... 181
10.11 HDLC O
VERHEAD
C
ONTROLLER
.................................................................................................181
10.11.1 General Description ........................................................................................................................... 181
10.11.2 Features ............................................................................................................................................. 182
10.11.3 Transmit FIFO .................................................................................................................................... 182
10.11.4 Transmit HDLC Overhead Processor ................................................................................................ 182
10.11.5 Receive HDLC Overhead Processor ................................................................................................. 183
10.11.6 Receive FIFO ..................................................................................................................................... 184
10.12 T
RAIL
T
RACE
C
ONTROLLER
.........................................................................................................184
10.12.1 General Description ........................................................................................................................... 184
10.12.2 Features ............................................................................................................................................. 185
10.12.3 Functional Description........................................................................................................................ 185
10.12.4 Transmit Data Storage ....................................................................................................................... 186
10.12.5 Transmit Trace ID Processor ............................................................................................................. 186
10.12.6 Transmit Trail Trace Processing ........................................................................................................ 186
10.12.7 Receive Trace ID Processor .............................................................................................................. 186
10.12.8 Receive Trail Trace Processing ......................................................................................................... 186
10.12.9 Receive Data Storage ........................................................................................................................ 187
10.13 FEAC C
ONTROLLER
...................................................................................................................188
10.13.1 General Description ........................................................................................................................... 188
10.13.2 Features ............................................................................................................................................. 188
10.13.3 Functional Description........................................................................................................................ 188
10.14 L
INE
E
NCODER
/D
ECODER
...........................................................................................................190
10.14.1 General Description ........................................................................................................................... 190
5
嵌入式系统
