If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
−0.3V to +4V
LVCMOS/LVTTL Input Voltage
−0.3V to (V
CC
+0.3V)
LVCMOS/LVTTL Output Voltage
−0.3V to (V
CC
+0.3V)
LVDS Receiver Input Voltage
−0.3V to 3.9V
LVDS Driver Output Voltage
−0.3V to 3.9V
LVDS Output Short Circuit Duration
10 ms
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
+260°C
Maximum Package Power Dissipation Capacity Package
De-rating:
48L TQFP
1/θ
JA
°C/W above +25°C
DS90C241
θ
JA
θ
JC
45.8 (4L*); 75.4 (2L*) °C/W
21.0°C/W
DS90C124
θ
JA
θ
JC
ESD Rating (HBM)
ESD Rating (ISO10605)
R
D
= 2 kΩ, C
S
= 330 pF
Contact
Discharge (D
OUT+
, D
OUT-
)
Air
Discharge (D
OUT+
, D
OUT-
)
±8 kV
±25 kV
45.4 (4L*); 75.0 (2L*)°C/W
21.1°C/W
*JEDEC
≥
±8 kV
DS90C241 meets ISO 10605
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Operating Free Air
Temperature (T
A
)
Clock Rate
Supply Noise
Min
3.0
−40
5
Nom
3.3
+25
Max
3.6
+105
35
±100
Units
V
°C
MHz
mV
P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
V
IH
V
IL
V
CL
Parameter
High Level Voltage
Low Level Input Voltage
Input Clamp Voltage
I
CL
= −18 mA
(Note 9)
Conditions
Pin/Freq.
Tx:
DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
Rx:
RPWDNB, RRFB,
REN
Tx:
DIN[23:0], TCLK,
TPWDNB, DEN, TRFB,
DCAOFF, DCBOFF,
VODSEL
Rx:
RPWDNB, RRFB,
REN
V
OH
V
OL
I
OS
I
OZ
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE
®
Output Current
I
OH
= −4 mA
I
OL
= +4 mA
V
OUT
= 0V
(Note 9)
RPWDNB, REN = 0V
V
OUT
= 0V or 2.4V
V
CM
= +1.2V
Rx:
ROUT[23:0], RCLK,
LOCK
Rx:
R
IN+
, R
IN−
−50
V
IN
= +2.4V,
V
CC
= 3.6V or 0V
V
IN
= 0V, V
CC
= 3.6V
±200
±200
Rx:
ROUT[23:0], RCLK,
LOCK
Min
2.0
GND
−0.8
Typ
Max
V
CC
0.8
−1.5
Units
V
V
V
LVCMOS/LVTTL DC SPECIFICATIONS
I
IN
Input Current
V
IN
= 0V or 3.6V
−10
±5
+10
µA
−20
2.3
±5
3.0
+20
V
CC
0.5
−110
+30
µA
V
V
mA
µA
GND 0.33
−40
−30
−70
±0.4
LVDS DC SPECIFICATIONS
V
TH
V
TL
I
IN
Differential Threshold High
Voltage
Differential Threshold Low
Voltage
Input Current
+50
mV
mV
µA
µA
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2
DS90C241/DS90C124
Symbol
V
OD
Parameter
Output Differential Voltage
(D
OUT+
)–(D
OUT−
)
Conditions
R
L
= 100Ω,
w/o Pre-emphasis
VODSEL = L
(Figure 10)
R
L
= 100Ω,
w/o Pre-emphasis
VODSEL = H
(Figure 10)
Pin/Freq.
Tx:
D
OUT+
, D
OUT−
Min
250
450
Typ
400
750
10
Max
600
1200
50
1.50
50
−8
Units
mV
mV
mV
V
mV
mA
ΔV
OD
V
OS
ΔV
OS
I
OS
Output Differential Voltage
Unbalance
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
R
L
= 100Ω,
w/o Pre-emphasis
R
L
= 100Ω,
w/o Pre-emphasis
R
L
= 100Ω,
w/o Pre-emphasis
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
−2
1.00 1.25
1
−7
−13
mA
I
OZ
TRI-STATE Output Current
TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
f = 35 MHz
R
L
= 100Ω
R
PRE
= OFF
VODSEL = H/L
Checker-board pattern
(Figure 1)
R
L
= 100Ω
R
PRE
= 6 kΩ
VODSEL = H/L
Checker-board pattern
(Figure 1)
f = 35 MHz
−15
±1
+15
µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins)
*Digital, PLL, and Analog VDDs
I
CCT
Serializer (Tx)
Total Supply Current
(includes load current)
40
65
mA
45
70
mA
Serializer (Tx)
Total Supply Current
(includes load current)
R
L
= 100Ω
R
PRE
= OFF
VODSEL = H/L
R
L
= 100Ω
R
PRE
= 6 kΩ
VODSEL = H/L
Random pattern
f = 35 MHz
40
f = 35 MHz
45
70
mA
65
mA
I
CCTZ
I
CCR
Serializer (Tx)
Supply Current Power-down
Deserializer (Rx)
Total Supply Current
(includes load current)
Deserializer (Rx)
Total Supply Current
(includes load current)
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
C
L
= 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
C
L
= 8 pF LVCMOS Output
Random pattern
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R
IN+
/ R
IN-
= 0V)
f = 35 MHz
800
µA
85
f = 35 MHz
80
mA
mA
I
CCRZ
Deserializer (Rx)
Supply Current Power-down
50
µA
3
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DS90C241/DS90C124
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t
TCP
t
TCIH
t
TCIL
t
CLKT
t
JIT
Parameter
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 4)
(Note 10)
(Figure 5)
Conditions
Min
28.6
Typ
T
Max
200
Units
ns
ns
ns
ns
ps
(RMS)
0.4T 0.5T 0.6T
0.4T 0.5T 0.6T
3
6
33
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t
LLHT
t
LHLT
t
DIS
t
DIH
t
HZD
t
LZD
t
ZHD
t
ZLD
t
PLD
t
SD
Parameter
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
DIN (23:0) Setup to TCLK
DIN (23:0) Hold from TCLK
DOUT ± HIGH to TRI-STATE Delay
DOUT ± LOW to TRI-STATE Delay
DOUT ± TRI-STATE to HIGH Delay
DOUT ± TRI-STATE to LOW Delay
Serializer PLL Lock Time
Serializer Delay
R
L
= 100Ω,
(
Figure 7)
R
L
= 100Ω,
(
Figure 8)
VODSEL = L, TRFB = H
R
L
= 100Ω,
(
Figure 8)
VODSEL = L, TRFB = L
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
5–35 MHz
(Figure 9)
(Notes 9, 10, 14)
0.75
3.5T + 2.85
3.5T + 2.85
Conditions
R
L
= 100Ω,
(
Figure 3)
C
L
= 10 pF to GND
VODSEL = L
R
L
= 100Ω,
C
L
= 10 pF to GND
(Note 9)
R
L
= 100Ω,
C
L
= 10 pF to GND
(Figure 6)
(Note 5)
5
5
15
15
200
200
10
3.5T
+ 10
3.5T
+ 10
Min
Typ
Max
0.6
0.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
UI
(Note 11)
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t
RCP
t
RDC
t
CLH
t
CHL
t
ROS
t
ROH
t
ROS
t
ROH
Parameter
Receiver
out
Clock Period
RCLK Duty Cycle
LVCMOS
Low-to-High
Transition Time
LVCMOS
High-to-Low
Transition Time
ROUT
(7:0)
Setup
Data to
RCLK (Group 1)
ROUT
(7:0)
Hold
Data to RCLK
(Group 1)
ROUT
(15:8)
Setup
Data to
RCLK (Group 2)
ROUT
(15:8)
Hold
Data to
RCLK (Group 2)
(Figure 15)
ROUT [15:8],
LOCK
C
L
= 8 pF
(lumped load)
(Figure 11)
(Note 9)
(Figure 15)
Conditions
t
RCP
= t
TCP
(Note 9)
Pin/Freq.
RCLK
RCLK
ROUT [23:0],
LOCK, RCLK
Min
28.6
45
50
2.5
2.5
ROUT [7:0]
(0.40)*
(29/56)*t
RCP
t
RCP
(0.40)*
(27/56)*t
RCP
t
RCP
(0.40)*
t
RCP
(0.40)*
t
RCP
0.5*t
RCP
0.5*t
RCP
Typ
Max
200
55
3.5
3.5
Units
ns
%
ns
ns
ns
ns
ns
ns
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4
DS90C241/DS90C124
Symbol
t
ROS
t
ROH
t
HZR
t
LZR
t
ZHR
t
ZLR
t
DD
t
DRDL
RxIN_TOL_L
Parameter
ROUT
(23:16)
Setup
Data to
RCLK (Group 3)
ROUT
(23:16)
Hold
Data to
RCLK (Group 3)
HIGH
to TRI-STATE Delay
LOW
to TRI-STATE Delay
TRI-STATE to
HIGH
Delay
TRI-STATE to
LOW
Delay
Deserializer Delay
Deserializer PLL Lock Time
from Powerdown
Receiver INput TOLerance
Left,
Conditions
(Figure 15)
Pin/Freq.
ROUT [23:16]
Min
Typ
Max
Units
ns
ns
(0.40)*
(27/56)*t
RCP
t
RCP
(0.40)*
(29/56)*t
RCP
t
RCP
(Figure 13)
ROUT [23:0],
RCLK, LOCK
3
3
3
3
10
10
10
10
ns
ns
ns
ns
ns
ms
ms
UI
UI
(Figure 12)
(Figure 14)
(Notes 8, 9)
(Figure 16)
(Notes 7, 9, 11)
(Figure 16)
(Notes 7, 9, 11)
RCLK
5 MHz
35 MHz
5 MHz–35 MHz
5 MHz–35 MHz
[4+(3/56)]T [4+(3/56)]T
+5.9
+14
5
5
50
50
0.25
0.25
RxIN_TOL_R
Receiver INput TOLerance
Right,
Note 1:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2:
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3:
Typical values represent most likely parametric norms at V
CC
= 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4:
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD,
ΔVOD,
VTH and VTL which are differential voltages.
Note 5:
When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6:
t
DRDL
is the time required by the deserializer to obtain lock when exiting powerdown mode. t
DRDL
is specified with an external synchronization pattern.
Note 7:
RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 8:
The Deserializer PLL lock time (t
DRDL
) may vary depending on input data patterns and the number of transitions within the pattern.
Note 9:
Specification is guaranteed by characterization and is not tested in production.
Note 10:
t
JIT
(@BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
Note 11:
UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 12:
Figures 1, 2, 8, 12, 14
show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 13:
Figures 5, 15
show a rising edge data strobe (TCLK IN/RCLK OUT).
