Freescale Semiconductor
Technical Data
DSP56321
Rev. 11, 2/2005
DSP56321
24-Bit Digital Signal Processor
3
16
6
6
Memory Expansion Area
Program
RAM
32 K
×
24 bits
or
31 K
×
24 bits
and
Instruction
Cache
1024
×
24 bits
PM_EB
SCI
Triple
Timer
HI08
ESSI
EFCOP
X Data
RAM
80 K
×
24 bits
Y Data
RAM
80 K
×
24 bits
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Management
JTAG
OnCE™
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
10
Control
The DSP56321 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
Internal
Data
Bus
Switch
24
Data
What’s New?
Rev. 11 includes the following
changes:
•
Adds lead-free packaging and
part numbers.
Clock
PLL
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
DE
Figure 1.
DSP56321 Block Diagram
The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and
home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-
compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller
(see
Figure 1).
The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550
MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and
independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall
enhanced performance and signal quality with no impact on channel throughput or total channel support. This
device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
© Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.
Table of Contents
Data Sheet Conventions .......................................................................................................................................ii
Features...............................................................................................................................................................iii
Target Applications ............................................................................................................................................. iv
Product Documentation .......................................................................................................................................v
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
Power ................................................................................................................................................................1-3
Ground ..............................................................................................................................................................1-3
Clock.................................................................................................................................................................1-3
External Memory Expansion Port (Port A) ......................................................................................................1-4
Interrupt and Mode Control ..............................................................................................................................1-6
Host Interface (HI08)........................................................................................................................................1-7
Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-10
Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-11
Serial Communication Interface (SCI) ...........................................................................................................1-12
Timers .............................................................................................................................................................1-13
JTAG and OnCE Interface ..............................................................................................................................1-14
Maximum Ratings.............................................................................................................................................2-1
Thermal Characteristics ....................................................................................................................................2-2
DC Electrical Characteristics............................................................................................................................2-2
AC Electrical Characteristics............................................................................................................................2-3
Package Description .........................................................................................................................................3-2
MAP-BGA Package Mechanical Drawing .....................................................................................................3-10
Thermal Design Considerations........................................................................................................................4-1
Electrical Design Considerations......................................................................................................................4-2
Power Consumption Considerations.................................................................................................................4-3
Input (EXTAL) Jitter Requirements .................................................................................................................4-4
Chapter 2
Specifications
2.1
2.2
2.3
2.4
Chapter 3
Packaging
3.1
3.2
Chapter 4
Design Considerations
4.1
4.2
4.3
4.4
Appendix A
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
“asserted”
“deasserted”
Examples:
Indicates a signal that is active when pulled low (For example, the
RESET
pin is active when
low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Signal State
PIN
True
Asserted
PIN
False
Deasserted
PIN
True
Asserted
PIN
False
Deasserted
Note:
Values for
V
IL
,
V
OL
,
V
IH
, and
V
OH
are defined by individual product specifications.
DSP56321 Technical Data, Rev. 11
ii
Freescale Semiconductor
Features
Table 1
lists the features of the DSP56321 device.
Table 1.
DSP56321 Features
Feature
Description
• 275 million multiply-accumulates per second (MMACS) (550 MMACS using the EFCOP in filtering
applications) with a 275 MHz clock at 1.6 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24
×
24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program control unit (PCU) with position independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
test access port (TAP)
• Internal 24
×
24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 275 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
High-Performance
DSP56300 Core
Enhanced Filter
Coprocessor (EFCOP)
Internal Peripherals
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
iii
Table 1.
DSP56321 Features (Continued)
Feature
Description
• 192
×
24-bit bootstrap ROM
• 192 K
×
24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM
Size
32 K
×
24-bit
31 K
×
24-bit
40 K
×
24-bit
39 K
×
24-bit
48 K
×
24-bit
47 K
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size*
80 K
×
24-bit
80 K
×
24-bit
76 K
×
24-bit
76 K
×
24-bit
72 K
×
24-bit
72 K
×
24-bit
64 K
×
24-bit
64 K
×
24-bit
60 K
×
24-bit
60 K
×
24-bit
56 K
×
24-bit
56 K
×
24-bit
48 K
×
24-bit
48 K
×
24-bit
40 K
×
24-bit
40 K
×
24-bit
Y Data RAM
Size*
80 K
×
24-bit
80 K
×
24-bit
76 K
×
24-bit
76 K
×
24-bit
72 K
×
24-bit
72 K
×
24-bit
64 K
×
24-bit
64 K
×
24-bit
60 K
×
24-bit
60 K
×
24-bit
56 K
×
24-bit
56 K
×
24-bit
48 K
×
24-bit
48 K
×
24-bit
40 K
×
24-bit
40 K
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
MSW2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MSW1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MSW0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
:
Internal Memories
64 K
×
24-bit
63 K
×
24-bit
72 K
×
24-bit
71 K
×
24-bit
80 K
×
24-bit
79 K
×
24-bit
96 K
×
24-bit
95 K
×
24-bit
112 K
×
24-bit
111 K
×
24-bit
*Includes 12 K
×
24-bit shared memory (that is, 24 K total memory shared by the core and the EFCOP)
• Data memory expansion to two 256 K
×
24-bit word memory spaces using the standard external address
lines
• Program memory expansion to one 256 K
×
24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
•
•
•
•
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
External Memory
Expansion
Power Dissipation
Packaging
• Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Target Applications
DSP56321 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
•
•
•
•
•
•
•
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
Security encryption systems
Home entertainment systems
DSP resource boards
High-speed modem banks
IP telephony
DSP56321 Technical Data, Rev. 11
iv
Freescale Semiconductor
Product Documentation
The documents listed in
Table 2
are required for a complete description of the DSP56321 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2.
DSP56321 Documentation
Name
Description
Order Number
DSP56321RM
DSP56300FM
See the DSP56321 product website
DSP56321
Detailed functional description of the DSP56321 memory configuration,
Reference Manual
operation, and register programming
DSP56300 Family
Detailed description of the DSP56300 family processor core and instruction set
Manual
Application Notes
Documents describing specific applications or optimized device operation
including code examples
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
v
FPGA/CPLD
