ENC28J60
Stand-Alone Ethernet Controller with SPI Interface
Ethernet Controller Features
•
•
•
•
•
•
•
•
•
IEEE 802.3™ Compatible Ethernet Controller
Fully Compatible with 10/100/1000Base-T Networks
Integrated MAC and 10Base-T PHY
Supports One 10Base-T Port with Automatic
Polarity Detection and Correction
Supports Full and Half-Duplex modes
Programmable Automatic Retransmit on Collision
Programmable Padding and CRC Generation
Programmable Automatic Rejection of Erroneous
Packets
SPI Interface with Clock Speeds up to 20 MHz
Operational
•
•
•
•
•
•
Six Interrupt Sources and One Interrupt Output Pin
25 MHz Clock Input Requirement
Clock Out Pin with Programmable Prescaler
Operating Voltage of 3.1V to 3.6V (3.3V typical)
5V Tolerant Inputs
Temperature Range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• 28-Pin SPDIP, SSOP, SOIC, QFN Packages
Package Types
28-Pin SPDIP, SSOP, SOIC
V
CAP
V
SS
CLKOUT
INT
NC
(1)
SO
SI
SCK
CS
RESET
V
SSRX
TPIN-
TPIN+
RBIAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
LEDA
LEDB
V
DDOSC
OSC2
OSC1
V
SSOSC
V
SSPLL
V
DDPLL
V
DDRX
V
SSTX
TPOUT+
TPOUT-
V
DDTX
Buffer
•
•
•
•
8-Kbyte Transmit/Receive Packet Dual Port SRAM
Configurable Transmit/Receive Buffer Size
Hardware Managed Circular Receive FIFO
Byte-Wide Random and Sequential Access with
Auto-Increment
• Internal DMA for Fast Data Movement
• Hardware Assisted Checksum Calculation for
Various Network Protocols
ENC28J60
• Supports Unicast, Multicast and Broadcast
Packets
• Programmable Receive Packet Filtering and Wake-up
Host on Logical AND or OR of the Following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by
64-bit Hash Table
- Programmable Pattern Matching of up to
64 bytes at user-defined offset
INT
CLKOUT
V
SS
V
CAP
V
DD
LEDA
LEDB
28 27 26 25 24 23 22
Medium Access Controller (MAC)
Features
28-Pin QFN
(2)
NC
(1)
SO
SI
SCK
CS
RESET
V
SSRX
1
2
3
4
5
6
7
ENC28J60
21
20
19
18
17
16
15
V
DDOSC
OSC2
OSC1
V
SSOSC
V
SSPLL
V
DDPLL
V
DDRX
8 9 10 11 12 13 14
• Loopback mode
• Two Programmable LED Outputs for LINK, TX,
RX, Collision and Full/Half-Duplex Status
Note 1:
Reserved pin; always leave disconnected.
2:
The back pad on QFN devices should be connected
to Vss.
2006-2012 Microchip Technology Inc.
.
TPOUT-
TPOUT+
V
SSTX
TPIN-
TPIN+
RBIAS
V
DDTX
Physical Layer (PHY) Features
DS39662E-page 1
ENC28J60
Table of Contents
1.0 Overview ...................................................................................................................................................................................... 3
2.0 External Connections ................................................................................................................................................................... 5
3.0 Memory Organization ................................................................................................................................................................. 11
4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 25
5.0 Ethernet Overview ...................................................................................................................................................................... 31
6.0 Initialization................................................................................................................................................................................. 33
7.0 Transmitting and Receiving Packets .......................................................................................................................................... 39
8.0 Receive Filters............................................................................................................................................................................ 47
9.0 Duplex Mode Configuration and Negotiation.............................................................................................................................. 53
10.0 Flow Control ............................................................................................................................................................................... 55
11.0 Reset .......................................................................................................................................................................................... 59
12.0 Interrupts .................................................................................................................................................................................... 63
13.0 Direct Memory Access Controller ............................................................................................................................................... 71
14.0 Power-Down ............................................................................................................................................................................... 73
15.0 Built-in Self-Test Controller ........................................................................................................................................................ 75
16.0 Electrical Characteristics ............................................................................................................................................................ 79
17.0 Packaging Information................................................................................................................................................................ 83
Appendix A: Revision History............................................................................................................................................................... 93
The Microchip Web Site ....................................................................................................................................................................... 95
Customer Change Notification Service ................................................................................................................................................ 95
Customer Support ................................................................................................................................................................................ 95
Reader Response ................................................................................................................................................................................ 96
Product Identification System............................................................................................................................................................... 99
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DS39662E-page 2
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2006-2012 Microchip Technology Inc.
ENC28J60
1.0
OVERVIEW
The ENC28J60 is a stand-alone Ethernet controller
with an industry standard Serial Peripheral Interface
(SPI). It is designed to serve as an Ethernet network
interface for any controller equipped with SPI.
The ENC28J60 meets all of the IEEE 802.3 specifica-
tions. It incorporates a number of packet filtering
schemes to limit incoming packets. It also provides an
internal DMA module for fast data throughput and hard-
ware assisted checksum calculation, which is used in
various network protocols. Communication with the
host controller is implemented via an interrupt pin and
the SPI, with clock rates of up to 20 MHz. Two
dedicated pins are used for LED link and network
activity indication.
A simple block diagram of the ENC28J60 is shown in
Figure 1-1.
A typical application circuit using the device
is shown in
Figure 1-2.
With the ENC28J60, two pulse
transformers and a few passive components are all that
are required to connect a microcontroller to an Ethernet
network.
The ENC28J60 consists of seven major functional
blocks:
1.
An SPI interface that serves as a communica-
tion channel between the host controller and the
ENC28J60.
Control registers which are used to control and
monitor the ENC28J60.
A dual port RAM buffer for received and
transmitted data packets.
An arbiter to control the access to the RAM buf-
fer when requests are made from DMA, transmit
and receive blocks.
The bus interface that interprets data and
commands received via the SPI interface.
The MAC (Medium Access Control) module that
implements IEEE 802.3 compliant MAC logic.
The PHY (Physical Layer) module that encodes
and decodes the analog data that is present on
the twisted-pair interface.
2.
3.
4.
5.
6.
7.
The device also contains other support blocks, such as
the oscillator, on-chip voltage regulator, level translators
to provide 5V tolerant I/Os and system control logic.
FIGURE 1-1:
ENC28J60 BLOCK DIAGRAM
Buffer
8 Kbytes
Dual Port RAM
RX
MAC
RXBM
TPOUT+
RXF (Filter)
ch0
MII
Interface
TX
TPOUT-
LEDA
LEDB
CLKOUT
Control
Registers
Arbiter
ch1
ch0
DMA &
Checksum
TX
PHY
TPIN+
TPIN-
ch1
INT
Bus Interface
TXBM
Flow Control
Host Interface
MIIM
Interface
RX
RBIAS
CS
(1)
SI
(1)
SO
SCK
(1)
SPI
System Control
Power-on
Reset
Voltage
Regulator
25 MHz
Oscillator
OSC1
OSC2
RESET
(1)
Note 1:
These pins are 5V tolerant.
V
CAP
2006-2012 Microchip Technology Inc.
.
DS39662E-page 3
ENC28J60
FIGURE 1-2:
TYPICAL ENC28J60 BASED INTERFACE
MCU
I/O
SDO
SDI
SCK
CS
SI
SO
SCK
TX/RX
Buffer
MAC
PHY
LEDA
LEDB
ENC28J60
TPIN+/-
TPOUT+/-
RJ45
ETHERNET
TRANSFORMER
INT
X
INT
TABLE 1-1:
Pin Name
V
CAP
PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Type
P
Buffer
Type
—
Description
2.5V output from internal regulator. A low Equivalent Series Resistance (ESR)
capacitor, with a typical value of 10 µF and a minimum value of 1 µF to ground,
must be placed on this pin.
Ground reference.
Programmable clock output pin.
(1)
INT interrupt output pin.
(2)
Reserved function; always leave unconnected.
Data out pin for SPI interface.
(2)
Data in pin for SPI interface.
(3)
Clock in pin for SPI interface.
(3)
Chip select input pin for SPI interface.
(3,4)
Active-low device Reset input.
(3,4)
Ground reference for PHY RX.
Differential signal input.
Differential signal input.
Bias current pin for PHY. Must be tied to ground via a resistor (refer to
Section 2.4 “Magnetics, Termination and Other External Components”
for details).
Positive supply for PHY TX.
Differential signal output.
Differential signal output.
Ground reference for PHY TX.
Positive 3.3V supply for PHY RX.
Positive 3.3V supply for PHY PLL.
Ground reference for PHY PLL.
Ground reference for oscillator.
Oscillator input.
Oscillator output.
Positive 3.3V supply for oscillator.
LEDB driver pin.
(5)
LEDA driver pin.
(5)
Positive 3.3V supply.
SPDIP,
SOIC, SSOP
1
QFN
25
V
SS
CLKOUT
INT
NC
SO
SI
SCK
CS
RESET
V
SSRX
TPIN-
TPIN+
RBIAS
2
3
4
5
6
7
8
9
10
11
12
13
14
26
27
28
1
2
3
4
5
6
7
8
9
10
P
O
O
O
O
I
I
I
I
P
I
I
I
—
—
—
—
—
ST
ST
ST
ST
—
ANA
ANA
ANA
V
DDTX
TPOUT-
TPOUT+
V
SSTX
V
DDRX
V
DDPLL
V
SSPLL
V
SSOSC
OSC1
OSC2
V
DDOSC
LEDB
LEDA
V
DD
Legend:
Note 1:
2:
3:
4:
5:
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P
O
O
P
P
P
P
P
I
O
P
O
O
P
—
—
—
—
—
—
—
—
ANA
—
—
—
—
—
I = Input, O = Output, P = Power, ANA = Analog Signal Input, ST = Schmitt Trigger
Pins have a maximum current capacity of 8 mA.
Pins have a maximum current capacity of 4 mA.
Pins are 5V tolerant.
Pins have an internal weak pull-up to V
DD
.
Pins have a maximum current capacity of 12 mA.
DS39662E-page 4
.
2006-2012 Microchip Technology Inc.
ENC28J60
2.0
2.1
EXTERNAL CONNECTIONS
Oscillator
2.2
Oscillator Start-up Timer
The ENC28J60 is designed to operate at 25 MHz with a
crystal connected to the OSC1 and OSC2 pins. The
ENC28J60 design requires the use of a parallel reso-
nance crystal. Use of a series resonance crystal may give
a frequency out of the crystal manufacturer specifications.
A typical oscillator circuit is shown in
Figure 2-1.
The ENC28J60 may also be driven by an external clock
source connected to the OSC1 pin as shown in
Figure 2-2.
The ENC28J60 contains an Oscillator Start-up Timer
(OST) to ensure that the oscillator and integrated PHY
have stabilized before use. The OST does not expire
until 7500 OSC1 clock cycles (300
s)
pass after
Power-on Reset or wake-up from Power-Down mode
occurs. During the delay, all Ethernet registers and buf-
fer memory may still be read and written to through the
SPI bus. However, software should not attempt to
transmit any packets (set ECON1.TXRTS), enable
reception of packets (set ECON1.RXEN) or access any
MAC, MII or PHY registers during this period.
When the OST expires, the CLKRDY bit in the ESTAT
register will be set. The application software should poll
this bit as necessary to determine when normal device
operation can begin.
Note:
After a Power-on Reset, or the ENC28J60
is removed from Power-Down mode, the
CLKRDY bit must be polled before
transmitting packets, enabling packet
reception or accessing any MAC, MII or
PHY registers.
FIGURE 2-1:
CRYSTAL OSCILLATOR
OPERATION
ENC28J60
OSC1
C
1
XTAL
R
F
(2)
C
2
Note 1:
2:
R
S
(1)
OSC2
To Internal Logic
A series resistor, R
S
, may be required for AT
strip cut crystals.
The feedback resistor, R
F
, is typically in the
range of 2 to 10 M.
FIGURE 2-2:
EXTERNAL CLOCK
SOURCE
(1)
ENC28J60
3.3V Clock from
External System
OSC1
Open
(2)
Note 1:
2:
OSC2
Duty cycle restrictions must be observed.
A resistor to ground may be used to reduce
system noise. This may increase system
current.
2006-2012 Microchip Technology Inc.
.
DS39662E-page 5
FPGA/CPLD
