EP7312 Data Sheet
FEATURES
ARM 720T Processor
— ARM7TDMI CPU Operating at Speeds of 74 and
90 MHz
— 8 kBytes of Four-way Set-associative Cache
— MMU with 64-entry TLB
— Thumb™ Code Support Enabled
Ultra low power
— 90 mW at 74 MHz Typical
— 108 mW at 90 MHz Typical
— <.03 mW in the Standby State
Advanced Audio Decoder/decompression Capability
— Supports bit streams with adaptive bit rates.
— Allows for support of multiple audio decompression
algorithms (MP3, WMA, AAC, Audible, etc.).
®
High-performance,
Low-power, System-on-chip
with SDRAM & Enhanced
Digital Audio Interface
OVERVIEW
The Cirrus Logic
™
EP7312 is designed for ultra-low-power
portable and line-powered applications such as portable
consumer entertainment devices, home and car audio juke box
systems, and general purpose industrial control applications, or
any device that features the added capability of digital audio
compression & decompression. The core-logic functionality of
the device is built around an ARM720T processor with
8 kBytes of four-way set-associative unified cache and a write
buffer. Incorporated into the ARM720T is an enhanced
memory management unit (MMU) which allows for support of
sophisticated operating systems like Microsoft
®
Windows
®
CE and Linux
®
.
(cont.)
(cont.)
BLOCK DIAGRAM
Digital
Audio
Interface
EPB Bus
Clocks &
Tim ers
SERIAL PORTS
Serial
Interface
Power
Managem ent
ARM720T
ICE-JTAG
ARM 7TDM I CPU Core
Interrupts,
PW M & GPIO
USER INTERFACE
(2) UARTs
w/ IrDA
8 KB
Cache
Boot
ROM
W rite
Buffer
Bus
Bridge
MMU
Keypad&
Touch
Screen I/F
Internal Data Bus
M em ory Controller
M averickKey
TM
SRAM I/F
SDRAM I/F
On-chip SRAM
48 KB
LCD
Controller
MEMORY and STORAGE
Copyright Cirrus Logic, Inc. 2011
http://www.cirrus.com
(All Rights Reserved)
MAR ‘11
DS508F2
EP7312
High-Performance, Low-Power System on Chip
FEATURES
(cont)
48 KBytes of On-chip SRAM
MaverickKey
™
IDs
— 32-bit unique ID can be used for DRM-compliant 128-
bit random ID.
Available in 74 and 90 MHz clock speeds.
LCD controller
— Interfaces directly to a single-scan panel monochrome
STN LCD.
— Interfaces to a single-scan panel color STN LCD with
minimal external glue logic.
Full JTAG Boundary Scan and Embedded ICE
Support
Integrated Peripheral Interfaces
— 32-bit SDRAM Interface, Up to 2 External Banks
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Digital Audio Interface provides glueless interface to
low-power DACs, ADCs, and CODECs.
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 88 Keypad Scanner
— 27 General-purpose Input/Output Pins
— Dedicated LED Flasher Pin from the RTC
Internal Peripherals
— Two 16550-compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two General-purpose 16-bit Timers
— Interrupt Controller
— Boot ROM
Package
— 208-Pin LQFP
— 256-Ball PBGA
The fully static EP7312 is optimized for low power
dissipation and is fabricated using a 0.25 micron CMOS
process.
OVERVIEW
(cont.)
The EP7312 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
operating, idle and standby.
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
The EP7312 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, high quality ADCs, DACs, or
CODECs such as the Cirrus Logic CS53L32A, CS43L42, and
CS42L50 are easily added to an EP73xx design via the DAI.
Some of these devices feature digital bass and treble boost,
digital volume control and compressor-limiter functions.
Simply by adding desired memory and peripherals to the
highly integrated EP7312 completes a low-power system
solution. All necessary interface logic is integrated on-chip.
2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES ...........................................................................................................................................1
OVERVIEW ...........................................................................................................................................1
FEATURES
(cont) .......................................................................................................................................................2
OVERVIEW
(cont.) ......................................................................................................................................................2
Description of the EP7312’s Components, Functionality, and Interfaces ....................................6
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID .....................................................................................................................................6
Memory Interfaces .................................................................................................................................................6
Digital Audio Capability .........................................................................................................................................7
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7
Digital Audio Interface (DAI) ..................................................................................................................................7
CODEC Interface ..................................................................................................................................................8
SSI2 Interface ........................................................................................................................................................8
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
64-Key Keypad Interface .......................................................................................................................................8
Interrupt Controller ................................................................................................................................................9
Real-Time Clock ....................................................................................................................................................9
PLL and Clocking ..................................................................................................................................................9
DC-to-DC Converter Interface (PWM) .................................................................................................................10
Timers .................................................................................................................................................................10
General Purpose Input/Output (GPIO) ................................................................................................................10
Hardware Debug Interface ..................................................................................................................................10
LED Flasher ........................................................................................................................................................10
Internal Boot ROM ...............................................................................................................................................10
Packaging ............................................................................................................................................................10
Pin Multiplexing ................................................................................................................................................... 11
System Design ....................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................13
Absolute Maximum Ratings .................................................................................................................................13
Recommended Operating Conditions .................................................................................................................13
DC Characteristics ..............................................................................................................................................13
Timings ...............................................................................................................................................15
Timing Diagram Conventions ....................................................................................................................15
Timing Conditions ......................................................................................................................................15
SDRAM Interface ................................................................................................................................................16
SDRAM Load Mode Register Cycle ..........................................................................................................17
SDRAM Burst Read Cycle .........................................................................................................................18
SDRAM Burst Write Cycle .........................................................................................................................19
SDRAM Refresh Cycle ..............................................................................................................................20
Static Memory ......................................................................................................................................................21
Static Memory Single Read Cycle .............................................................................................................22
Static Memory Single Write Cycle ..............................................................................................................23
Static Memory Burst Read Cycle ...............................................................................................................24
Static Memory Burst Write Cycle ...............................................................................................................25
SSI1 Interface ......................................................................................................................................................26
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
3
EP7312
High-Performance, Low-Power System on Chip
SSI2 Interface ..................................................................................................................................................... 27
LCD Interface ...................................................................................................................................................... 28
JTAG Interface .................................................................................................................................................... 29
Packages ........................................................................................................................................... 30
208-Pin LQFP Package Characteristics ............................................................................................................. 30
208-Pin LQFP Pin Diagram ................................................................................................................................ 31
208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32
256-Ball PBGA Package Characteristics ............................................................................................................ 38
256-Ball PBGA Pinout (Top View) ....................................................................................................................... 39
256-Ball PBGA Ball Listing ................................................................................................................................. 40
JTAG Boundary Scan Signal Ordering ............................................................................................................... 45
CONVENTIONS ................................................................................................................................. 50
Acronyms and Abbreviations .............................................................................................................................. 50
Units of Measurement ......................................................................................................................................... 50
General Conventions .......................................................................................................................................... 51
Pin Description Conventions ............................................................................................................................... 51
Ordering Information ....................................................................................................................... 52
Environmental, Manufacturing, & Handling Information ............................................................. 52
Revision History .............................................................................................................................. 53
4
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Fully-Configured EP7312-Based System ...................................................................................................12
Figure 2. Legend for Timing Diagrams .........................................................................................................................15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17
Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18
Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19
Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24
Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25
Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26
Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27
Figure 13. LCD Controller Timing Measurement ..........................................................................................................28
Figure 14. JTAG Timing Measurement .........................................................................................................................29
Figure 15. 208-Pin LQFP Package Outline Drawing ....................................................................................................30
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................31
Figure 17. 256-Ball PBGA Package ..............................................................................................................................38
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6
Table 2. Static Memory Interface Pin Assignments ........................................................................................................6
Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7
Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table 5. DAI Interface Pin Assignments .........................................................................................................................7
Table 6. CODEC Interface Pin Assignments ..................................................................................................................8
Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8
Table 8. Serial Interface Pin Assignments ......................................................................................................................8
Table 9. LCD Interface Pin Assignments ........................................................................................................................8
Table 10. Keypad Interface Pin Assignments .................................................................................................................9
Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9
Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9
Table 13. PLL and Clocking Pin Assignments ................................................................................................................9
Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10
Table 15. General Purpose Input/Output Pin Assignments ..........................................................................................10
Table 16. Hardware Debug Interface Pin Assignments ................................................................................................10
Table 17. LED Flasher Pin Assignments ......................................................................................................................10
Table 18. DAI/SSI2/CODEC Pin Multiplexing ...............................................................................................................11
Table 19. Pin Multiplexing .............................................................................................................................................11
Table 20. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................32
Table 21. 256-Ball PBGA Ball Listing ...........................................................................................................................40
Table 22. JTAG Boundary Scan Signal Ordering .........................................................................................................45
Table 23. Acronyms and Abbreviations ........................................................................................................................50
Table 24. Unit of Measurement .....................................................................................................................................50
Table 25. Pin Description Conventions .........................................................................................................................51
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
5
