Data Sheet
FEATURES
Programmable frequency profile
No external components necessary
Output frequency up to 25 MHz
Preprogrammable frequency profile minimizes number of
DSP/microcontroller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Power-down mode: 20 µA
Power supply: 2.3 V to 5.5 V
Automotive temperature range: −40°C to +125°C
16-lead, Pb-free TSSOP
Programmable Frequency Scan
Waveform Generator
AD5932
GENERAL DESCRIPTION
The
AD5932
1
is a waveform generator offering a programmable
frequency scan. Utilizing embedded digital processing that
allows enhanced frequency control, the device generates
synthesized analog or digital frequency-stepped waveforms.
Because frequency profiles are preprogrammed, continuous
write cycles are eliminated, thereby freeing up valuable
DSP/microcontroller resources. Waveforms start from a known
phase and are incremented phase-continuously, which allows
phase shifts to be easily determined. Consuming only 6.7 mA,
the
AD5932
provides a convenient low power solution to
waveform generation.
The
AD5932
outputs each frequency in the range of interest for
a defined length of time and then steps to the next frequency in
the scan range. The length of time the device outputs a particular
frequency is preprogrammed, and the device increments the
frequency automatically; or, alternatively, the frequency is
incremented externally via the CTRL pin. At the end of the
range, the
AD5932
continues to output the last frequency until
the device is reset. The
AD5932
also offers a digital output via
the MSBOUT pin.
(continued on Page 3)
APPLICATIONS
Frequency scanning/radar
Network/impedance measurements
Incremental frequency stimulus
Sensory applications
Proximity and motion
FUNCTIONAL BLOCK DIAGRAM
DVDD
CAP/2.5V
DGND
INTERRUPT
STANDBY
AGND
AVDD
REGULATOR
VCC
2.5V
MCLK
SYNC
INCREMENT
CONTROLLER
DATA
INCR
24-BIT
PIPELINED
DDS CORE
BUFFER
MSBOUT
AD5932
BUFFER
SYNCOUT
CTRL
FREQUENCY
CONTROLLER
/
24
10-BIT
DAC
VOUT
DATA AND CONTROL
SERIAL INTERFACE
CONTROL
REGISTER
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
05416-001
FSYNC
SCLK
SDATA
Figure 1.
1
Protected by U.S. patent number 6747583.
Rev. C
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AD5932
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Specifications Test Circuit ........................................................... 5
Timing Specifications .................................................................. 6
Master Clock and Timing Diagrams ......................................... 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Frequency Profile........................................................................ 15
Data Sheet
Serial Interface ............................................................................ 15
Powering up the AD5932 .......................................................... 15
Programming the AD5932........................................................ 16
Setting Up the Frequency Scan................................................. 17
Activating and Controlling the Scan ....................................... 18
Outputs from the AD5932 ........................................................ 19
Applications..................................................................................... 20
Grounding and Layout .............................................................. 20
AD5932 to the ADSP-BF527 Interface .................................... 20
AD5932 to 68HC11/68L11 Interface ....................................... 20
AD5932 to 80C51/80L51 Interface .......................................... 21
AD5932 to DSP56002 Interface ............................................... 21
Evaluation Board ............................................................................ 22
Schematics ................................................................................... 23
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
4/2017—Rev. B to Rev. C
Changes to AD5932 to 68HC11/68L11 Interface Section ........ 20
11/2016—Rev. A to Rev. B
Changed ADSP-21xx to ADSP-BF527 ........................ Throughout
Changes to Features Section............................................................ 1
Changes to AD5932 to the ADSP-BF527 Interface Section and
Figure 34 .......................................................................................... 20
2/2012—Rev. 0 to Rev. A
Changes to Figure 21, Figure 22, Figure 23, Figure 24, and
Figure 25 .......................................................................................... 12
Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 13
4/2006—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
GENERAL DESCRIPTION
(continued from Page 1)
To program the
AD5932,
the user enters the start frequency, the
increment step size, the number of increments to be made, and
the time interval that the part outputs each frequency. The fre-
quency scan profile is initiated, started, and executed by toggling
the CTRL pin.
The
AD5932
is written to via a 3-wire serial interface that operates
at clock rates up to 40 MHz. The device operates with a power
supply from 2.3 V to 5.5 V.
AD5932
Note that the AVDD and DVDD are independent of each other
and can be operated from different voltages. The
AD5932
also
has a standby function that allows sections of the device that are
not in use to be powered down.
The
AD5932
is available in a 16-lead, Pb-free TSSOP.
Rev. C | Page 3 of 28
AD5932
SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate
VOUT Peak-to-Peak
VOUT Offset
V
MIDSCALE
VOUT TC
DC Accuracy
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range (SFDR)
Wide Band (0 to Nyquist)
Narrow Band (±200 kHz)
Clock Feedthrough
Wake-Up Time
OUTPUT BUFFER
VOUT Peak-to-Peak
Output Rise/Fall Time
2
VOLTAGE REFERENCE
Internal Reference
Reference TC
2
LOGIC INPUTS
2
Input Current
Input High Voltage, V
INH
Min
Y Grade
1
Typ
10
50
0.58
56
0.32
200
±1.5
±0.75
Max
Unit
Bits
MSPS
V
mV
V
ppm/°C
LSB
LSB
Test Conditions/Comments
Data Sheet
Internal 200 Ω resistor to GND
From 0 V to the trough of the waveform
Voltage at midscale output
53
60
−60
−56
−74
−50
1.7
−53
−52
−70
dB
dBc
dBc
dBc
dBc
ms
V
ns
V
ppm/°C
µA
V
V
V
V
V
V
pF
V
V
pF
V
mA
mA
mA
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/4096
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/4096
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/50
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/50
Up to 16 MHz out
From standby
Typically, square wave on MSBOUT and SYNCOUT
0
12
1.15
1.18
90
0.1
1.7
2.0
2.8
DVDD
1.26
±2
Input Low Voltage, V
INL
0.6
0.7
0.8
3
DVDD − 0.4 V
0.4
5
2.3
3.8
2.4
6.2
5.5
4
2.7
6.7
DVDD = 2.3 V to 2.7 V
DVDD = 2.7 V to 3.6 V
DVDD = 4.5 V to 5.5 V
DVDD = 2.3 V to 2.7 V
DVDD = 2.7 V to 3.6 V
DVDD = 4.5 V to 5.5 V
Input Capacitance, C
IN
LOGIC OUTPUTS
2
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State O/P Capacitance
POWER REQUIREMENTS
AVDD/DVDD
I
AA
I
DD
I
AA
+ I
DD
I
SINK
= 1 mA
I
SINK
= 1 mA
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/7
Rev. C | Page 4 of 28
Data Sheet
Parameter
Low Power Sleep Mode
Min
Y Grade
1
Typ
20
140
1
2
AD5932
Max
85
240
Unit
µA
µA
Test Conditions/Comments
Device is reset before putting into standby
All outputs powered down, MCLK = 0 V,
serial interface active
All outputs powered down, MCLK active,
serial interface active
Operating temperature range is as follows: Y version: −40°C to +125°C; typical specifications are at +25°C.
Guaranteed by design, not production tested.
SPECIFICATIONS TEST CIRCUIT
100nF
10nF
AVDD
10nF
CAP/2.5V
REGULATOR
COMP
12
AD5932
20pF
Figure 2. Test Circuit Used to Test the Specifications
Rev. C | Page 5 of 28
05416-002
SIN
ROM
10-BIT
DAC
VOUT
