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F71805

F71805F/FG

Super H/W Monitor + LPC IO

Release Date: Dec., 2006

Revision: V0.25P

F71805

Dec., 2006

V0.25P

F71805

F71805 Datasheet Revision History

Version

0.20P

0.21P

0.22P

Date

07/07/2004

07/28/2004

10/12/2004

0.23P

0.24P

04/15/2005

09/05/2006

0.25P

12/28/2006

Page

Revision History

Preliminary Release Version.

Revised PWM frequency range.

Added FANCTL Functions.

Revised Voltage Fault Enable Register (Index 29h bit 7).

Modified Application Circuit.

Added “Green Package” ordering information

Modified typo.

Added PWM Output frequency setting description.

Added Patent Note.

Please note that all data and specifications are subject to change without notice. All the trade marks of products and

companies mentioned in this data sheet belong to their respective owners.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Customers using or selling these products for use

in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such

improper use or sales.

F71805

Dec., 2006

V0.25P

F71805

Table of Contents

1. GENERAL DESCRIPTION .........................................................................................................................................................3

2. FEATURES ....................................................................................................................................................................................3

3. KEY SPECIFICATIONS ..............................................................................................................................................................5

4. PIN CONFIGURATION...............................................................................................................................................................5

5. PIN DESCRIPTION......................................................................................................................................................................6

5.1

5.2

5.3

5.4

5.5

5.6

5.7

OWER

.........................................................................................................................................................................6

LPC I

NTERFACE

.................................................................................................................................................................6

FDC ...................................................................................................................................................................................7

UART P

ORT AND

SIR.........................................................................................................................................................7

IEEE 1284 P

ARALLEL

ORT

...............................................................................................................................................9

H/W M

ONITOR

...................................................................................................................................................................9

LASH

ROM I

NTERFACE AND

GPIO.................................................................................................................................10

6. FUNCTION DESCRIPTION .....................................................................................................................................................11

6.1

6.2

6.3

6.4

6.5

OWER ON

TRAPPING

PTIONS

.......................................................................................................................................11

ARDWARE

ONITOR

......................................................................................................................................................11

FDC .................................................................................................................................................................................18

UART ..............................................................................................................................................................................19

ARALLEL

ORT

...............................................................................................................................................................19

7. REGISTER DESCRIPTION ......................................................................................................................................................19

7.1

LOBAL

ONTROL

EGISTERS

.........................................................................................................................................19

Software Reset Register



Index 02h............................................................................................................................ 20

Logic Device Number Register



Index 07h................................................................................................................. 20

Chip ID Register



Index 20h ....................................................................................................................................... 20

Chip ID Register



Index 21h ....................................................................................................................................... 20

Vendor ID Register



Index 23h ................................................................................................................................... 20

Vendor ID Register



Index 24h ................................................................................................................................... 20

Software Power Down Register



Index 25h ................................................................................................................ 20

UART IRQ Sharing Register



Index 26h .................................................................................................................... 21

Power On Trap Status Register



Index 27h ................................................................................................................. 21

Flash Control Register



Index 28h .............................................................................................................................. 21

Voltage Fault Enable Register



Index 29h................................................................................................................... 22

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

Dec., 2006

V0.25P

F71805

7.2

FDC R

EGISTER

.................................................................................................................................................................22

Logic Device Number Register........................................................................................................................................ 22

FDC Configuration Registers........................................................................................................................................... 23

Device Registers .............................................................................................................................................................. 25

7.2.1

7.2.2

7.2.3

7.3

UART 1 R

EGISTER

...........................................................................................................................................................40

Logic Device Number Register........................................................................................................................................ 40

UART 1 Configuration Register....................................................................................................................................... 41

Device Registers .............................................................................................................................................................. 42

7.3.1

7.3.2

7.3.3

7.4

UART 2 R

EGISTER

...........................................................................................................................................................45

Logic Device Number Register........................................................................................................................................ 45

UART 2 Configuration Registers ..................................................................................................................................... 45

Device Registers .............................................................................................................................................................. 47

7.4.1

7.4.2

7.4.3

7.5

ARALLEL

ORT

EGISTER

...............................................................................................................................................50

Logic Device Number Register........................................................................................................................................ 50

Parallel Port Configuration Registers............................................................................................................................... 50

Device Registers .............................................................................................................................................................. 51

7.5.1

7.5.2

7.5.3

7.6

ARDWARE

ONITOR

EGISTER

.....................................................................................................................................55

Logic Device Number Registers ...................................................................................................................................... 55

Hardware Monitor Configuration Registers ..................................................................................................................... 55

Device Registers .............................................................................................................................................................. 56

7.6.1

7.6.2

7.6.3

7.7

GPIO R

EGISTER

...............................................................................................................................................................76

Logic Device Number Register........................................................................................................................................ 76

GPIO Configuration Registers ......................................................................................................................................... 76

7.7.1

7.7.2

7.8

PME R

EGISTER

................................................................................................................................................................83

Logic Device Number Register........................................................................................................................................ 83

PME Configuration Registers .......................................................................................................................................... 83

7.8.1

7.8.2

8. PCB LAYOUT GUIDE................................................................................................................................................................85

9. ELECTRICAL CHARACTERISTIC........................................................................................................................................86

9.1

9.2

9.3

BSOLUTE

AXIMUM

ATINGS

.......................................................................................................................................86

DC C

HARACTERISTICS

.....................................................................................................................................................86

AC C

HARACTERISTICS

.....................................................................................................................................................87

10. ORDERING INFORMATION ................................................................................................................................................87

11. PACKAGE DIMENSIONS......................................................................................................................................................88

12. F71805 DEMO CIRCUIT ........................................................................................................................................................89

Dec., 2006

V0.25P

F71805

1. General Description

The F71805 is the featured IO chip specifically for PC system. Equipped with one IEEE 1284

parallel port, two UART port and FDC, F71805 provides SIR and Flash ROM Interface. Integrated with

hardware monitor, F71805 supports 9 sets of voltage sensor and 4 voltage fault signal outputs, 3 sets of

creative auto-controlling fans and 3 temperature sensor pins for the accurate current type temp.

measurement for CPU thermal diode or external transistors 2N3906.

The F71805 provides flexible features for multi-directional application. For instance, supports 24

GPIO pins which include pulse/level mode selection, IRQ sharing function also designed in UART

feature for particular usage and accurate current mode H/W monitor will be worth in measurement of

temperature. The F71805 is powered by 3.3V voltage, with the LPC interface in the package of 128-QFP.

2. Features

General Functions

Comply with LPC Spec. 1.0

Supports 24 GPIO pins. One set of GPIO supports High/Low Level/Pulse selection.

48 MHz clock input

FDC

Compatible with IBM PC AT disk drive systems

Variable write pre-compensation with track selectable capability

Support vertical recording format

DMA enable logic

16-byte data FIFOs

Support floppy disk drives and tape drives

Detects all overrun and under run conditions

Built-in address mark detection circuit to simplify the read electronics

Completely compatible with industry standard 82077

360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate

Support 3-mode FDD, and its Win95/98/2K/XP driver

UART

Two high-speed 16C550 compatible UART with 16-byte FIFOs

Fully programmable serial-interface characteristics

Dec., 2006

V0.25P

型号	F71805	F71805FG	F71805F
描述	Super H/W Monitor + LPC IO	Super H/W Monitor + LPC IO	Super H/W Monitor + LPC IO

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