FDMF5821DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
February 2014
FDMF5821DC – Smart Power Stage (SPS) Module
with Integrated Temperature Monitor
Features
Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip
Package with Flip Chip Low-Side MOSFET and
Dual Cool Architecture
High Current Handling: 60 A
3-State 5 V PWM Input Gate Driver
Dynamic Resistance Mode for Low-Side Drive
(LDRV) Slows Low-Side MOSFET during Negative
Inductor Current Switching
Auto DCM (Low-Side Gate Turn Off) Using
ZCD# Input
Thermal Monitor for Module Temperature Reporting
Programmable Thermal Shutdown (P_THDN)
HS-Short Detect Fault# / Shutdown
Dual Mode Enable / Fault# Pin
Internal Pull-Up and Pull-Down for ZCD# and
EN Inputs, respectively
Fairchild PowerTrench
®
MOSFETs for Clean
Voltage Waveforms and Reduced Ringing
Fairchild SyncFET™ Technology (Integrated
Schottky Diode) in Low-Side MOSFET
Integrated Bootstrap Schottky Diode
Optimized / Extremely Short Dead-Times
Under-Voltage Lockout (UVLO) on VCC
Optimized for Switching Frequencies up to 1.5 MHz
PWM Minimum Controllable On-Time: 30 ns
Low Shutdown Current: < 3 µA
Optimized FET Pair for Highest Efficiency:
10 ~ 15% Duty Cycle
Operating Ambient Temperature Range:
-40°C to +125°C
Fairchild Green Packaging and RoHS Compliance
Description
The SPS family is Fairchild’s next-generation, fully
optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, high-
frequency, synchronous buck, DC-DC applications. The
FDMF5821DC integrates a driver IC with a bootstrap
Schottky diode, two power MOSFETs, and a thermal
monitor into a thermally enhanced, ultra-compact, 5 mm
x 5 mm package.
With an integrated approach, the SPS switching power
stage is optimized for driver and MOSFET dynamic
performance, minimized system inductance, and power
MOSFET R
DS(ON)
. The SPS family uses Fairchild's high-
performance PowerTrench
®
MOSFET technology,
which reduces switch ringing, eliminating the need for a
snubber circuit in most buck converter applications.
A driver IC with reduced dead times and propagation
delays further enhances the performance. A thermal
monitor function warns of a potential over-temperature
situation. A programmable thermal shutdown function
turns off the driver if an over-temperature condition
occurs. The FDMF5821DC incorporates an Auto-DCM
Mode (ZCD#) for improved light-load efficiency. The
FDMF5821DC also provides a 3-state 5 V PWM input
for compatibility with a wide range of PWM controllers.
Applications
Servers and Workstations, V-Core and Non-V-Core
DC-DC Converters
Desktop and All-in-One Computers, V-Core and
Non-V-Core DC-DC Converters
High-Performance Gaming Motherboards
High-Current DC-DC Point-of-Load Converters
Networking and Telecom Microprocessor Voltage
Regulators
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part Number
FDMF5821DC
Current Rating
60 A
Package
31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package
Top Mark
FDMF5821DC
© 2013 Fairchild Semiconductor Corporation
FDMF5821DC • Rev. 1.0.1
www.fairchildsemi.com
FDMF5821DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Application Diagram
Figure 1.
Typical Application Diagram
Functional Block Diagram
Figure 2.
Functional Block Diagram
© 2013 Fairchild Semiconductor Corporation
FDMF5821DC • Rev. 1.0.1
www.fairchildsemi.com
2
FDMF5821DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Pin Configuration
Figure 3.
Pin Configuration - Top View and Transparent View
Pin Definitions
Pin #
1
2
3
4, 32
5
6
7
8~11
12~15, 28
16~26
27, 33
29
30
31
Name
PWM
ZCD#
VCC
AGND
BOOT
NC
PHASE
VIN
PGND
SW
GL
PVCC
TMON
EN /
FAULT#
PWM input to the gate driver IC
Description
Enable input for the ZCD (Auto DCM) comparator
Power supply input for all analog control functions; this is the “quiet” V
CC
Analog ground for analog portions of the IC and for substrate
Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies
the charge to turn on the N-channel high-side MOSFET
No connect
Return connection for the boot capacitor, internally tied to SW node
Power input for the power stage
Power return for the power stage
Switching node junction between high-side and low-side MOSFETs; also input to the gate
driver SW node comparator and input into the ZCD comparator
Gate Low, Low-side MOSFET gate monitor
Power supply input for LS
(1)
gate driver and boot diode
Temperature monitoring & reporting / programmable thermal shutdown pin
Dual-functionality: enable input to the gate driver IC; FAULT# - internal pull-down
physically pulls this pin LOW upon detection of fault condition (HS
(2)
MOSFET short or
TMON signal exceeding 1.5 V)
Notes:
1. LS = Low Side.
2. HS = High Side.
© 2013 Fairchild Semiconductor Corporation
FDMF5821DC • Rev. 1.0.1
www.fairchildsemi.com
3
FDMF5821DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
A
= T
J
= 25°C
Symbol
V
CC
PV
CC
V
EN/FAULT#
V
PWM
V
ZCD#
V
GL
V
TMON
V
IN
V
PHASE
V
SW
V
BOOT
Supply Voltage
Drive Voltage
Output Enable / Disable
PWM Signal Input
ZCD Mode Input
Thermal Monitor
Power Input
PHASE
Switch Node Input
Bootstrap Supply
Parameter
Referenced to AGND
Referenced to AGND
Referenced to AGND
Referenced to AGND
Referenced to AGND
Referenced to AGND
Referenced to PGND, AGND
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 20 ns
Referenced to PGND, AGND (DC Only)
Referenced to PGND, AC < 20 ns
Referenced to AGND (DC Only)
Referenced to AGND, AC < 20 ns
Referenced to PVCC
f
SW
= 300 kHz, V
IN
=12 V, V
OUT
=1.8 V
f
SW
= 1 MHz, V
IN
=12 V, V
OUT
=1.8 V
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-5.0
-0.3
-5.0
-0.3
-5.0
-0.3
Max.
6.0
6.0
6.0
6.0
6.0
6.0
6.0
25.0
25.0
30.0
25.0
30.0
30.0
35.0
6.0
60
55
Unit
V
V
V
V
V
V
V
V
V
V
V
V
A
mA
°C/W
°C/W
°C
°C
°C
V
Low Gate Manufacturing Test Pin Referenced to AGND
V
BOOT-PHASE
Boot to PHASE Voltage
I
O(AV)(3)
I
FAULT
θ
J-A
θ
J-PCB
T
A
T
J
T
STG
ESD
Output Current
EN / FAULT# Sink Current
-0.1
7.0
12.4
1.8
Junction-to-Ambient Thermal Resistance
Junction-to-PCB Thermal Resistance (under Fairchild SPS Thermal Board)
Ambient Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Electrostatic Discharge
Protection
Human Body Model,
-55
-40
+125
+150
+150
ANSI/ESDA/JEDEC JS-001-2012
Charged Device Model, JESD22-C101
3000
2500
Note:
3. I
O(AV)
is rated with testing Fairchild’s SPS evaluation board at T
A
= 25°C with natural convection cooling. This
rating is limited by the peak SPS temperature, T
J
= 150°C, and varies depending on operating conditions and
PCB layout. This rating may be changed with different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
Operating Conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
PV
CC
Parameter
Control Circuit Supply Voltage
Gate Drive Circuit Supply Voltage
Min.
4.5
4.5
(4)
Typ.
5.0
5.0
Max.
5.5
5.5
(5)
Unit
V
V
V
IN
Output Stage Supply Voltage
4.5
12.0
16.0
V
Notes:
4. 3.0 V V
IN
is possible according to the application condition.
5. Operating at high V
IN
can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes
during MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at
or below the Absolute Maximum Ratings in the table above.
© 2013 Fairchild Semiconductor Corporation
FDMF5821DC • Rev. 1.0.1
www.fairchildsemi.com
4
FDMF5821DC — Smart Power Stage (SPS) Module with Integrated Temperature Monitor
Electrical Characteristics
Typical value is under V
IN
=12 V, V
CC
=PV
CC
=5 V and T
A
=T
J
=+ 25°C unless otherwise noted. Minimum / Maximum
values are under V
IN
=12 V, V
CC
=PV
CC
=5 V ± 10% and T
J
=T
A
=-40 ~ 125°C unless otherwise noted.
Symbol
Basic Operation
I
Q
I
SHDN
V
UVLO
V
UVLO_HYST
t
D_POR
Parameter
Quiescent Current
Shutdown Current
UVLO Threshold
UVLO Hysteresis
POR Delay to Enable IC
High-Level Input Voltage
Low-Level Input Voltage
Pull-Down Resistance
EN LOW Propagation Delay
EN HIGH Propagation Delay
Condition
I
Q
=I
VCC
+ I
PVCC
, EN=HIGH, PWM=LOW or
HIGH or Float (Non-Switching)
I
SHDN
=I
VCC
+ I
PVCC
, EN=GND
V
CC
Rising
V
CC
UVLO Rising to Internal PWM Enable
Min. Typ.
Max.
2
3
Unit
mA
µA
V
V
µs
V
3.5
3.8
0.4
4.1
20
EN Input
V
IH_EN
V
IL_EN
R
PLD_EN
t
PD_ENL
t
PD_ENH
2.0
0.8
250
PWM=GND, EN Going LOW to GL Going
LOW
PWM=GND, EN Going HIGH to GL
Going HIGH
2.0
0.8
10
PWM=GND, ZCD# Going LOW to GL
Going LOW (assume I
L
<=0)
PWM=GND, ZCD# Going HIGH to GL
Going HIGH
10
10
25
20
V
kΩ
ns
µs
ZCD# Input
V
IH_ZCD#
V
IL_ZCD#
I
PLU_ZCD#
t
PD_ZLGLL
t
PD_ZHGLH
High-Level Input Voltage
Low-Level Input Voltage
Pull-Up Current
ZCD# LOW Propagation Delay
ZCD# HIGH Propagation Delay
V
V
µA
ns
ns
PWM Input
R
UP_PWM
R
DN_PWM
V
IH_PWM
V
TRI_Window
V
IL_PWM
t
D_HOLD-OFF
V
HIZ_PWM
Pull-Up Impedance
Pull-Down Impedance
PWM High Level Voltage
3-State Window
PWM Low Level Voltage
3-State Shut-Off Time
3-State Open Voltage
PWM Minimum Controllable On-
Time
Minimum PWM HIGH Pulse Required for
SW Node to Switch from GND to VIN
Minimum GL HIGH Time when LOW
V
BOOT-SW
detected and PWM
LOW=<100 ns
PWM Going HIGH to GL Going LOW,
V
IH_PWM
to 90% GL
PWM Going LOW to GH
(6)
Going LOW,
V
IL_PWM
to 90% GH
PWM Going HIGH to GH Going HIGH,
V
IH_PWM
to 10% GH (ZCD#=LOW, I
L
=0,
Assumes DCM)
Typical Values: T
A
=T
J
=25°C,
V
CC
=PV
CC
=5 V,
Min. / Max. Values:
T
A
=T
J
=-40°C to 125°C,
V
CC
=PV
CC
=5 V ±10%
3.8
1.2
90
2.1
2.5
3.1
0.8
130
2.9
10
10
kΩ
kΩ
V
V
V
ns
V
Minimum Controllable On-Time
t
MIN_PWM_ON
30
ns
Forced Minimum GL HIGH Time
t
MIN_GL_HIGH
Forced Minimum GL HIGH
100
ns
PWM Propagation Delays & Dead Times (V
IN
=12 V, V
CC
=PV
CC
=5 V, f
SW
=1 MHz, I
OUT
=20 A, T
A
=25
°C
)
t
PD_PHGLL
t
PD_PLGHL
t
PD_PHGHH
PWM HIGH Propagation Delay
PWM LOW Propagation Delay
PWM HIGH Propagation Delay
(ZCD# Held LOW)
15
30
10
ns
ns
ns
Continued on the following page…
© 2013 Fairchild Semiconductor Corporation
FDMF5821DC • Rev. 1.0.1
www.fairchildsemi.com
5
