FM18L08
256Kb Bytewide FRAM Memory
Features
256K bit Ferroelectric Nonvolatile RAM
•
Organized as 32,768 x 8 bits
•
45 year Data Retention
•
Unlimited Read/Write Cycles
•
NoDelay™ Writes
•
Advanced High-Reliability Ferroelectric Process
Superior to Battery-Backed SRAM
•
No Battery Concerns
•
Monolithic Reliability
•
True Surface Mount Solution, No Rework Steps
•
Superior for Moisture, Shock, and Vibration
•
Resistant to Negative Voltage Undershoots
SRAM & EEPROM Compatible
•
JEDEC 32Kx8 SRAM & EEPROM pinout
•
70 ns Access Time
•
140 ns Cycle Time
Low Power Operation
•
3.0V to 3.65V Operation
•
15 mA Active Current
•
15
µA
Standby Current
Description
The FM18L08 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and reads and writes like a RAM. It
provides data retention for 45 years while eliminating
the reliability concerns, functional disadvantages and
system design complexities of battery-backed SRAM
(BBSRAM). Fast write timing and high write
endurance make FRAM superior to other types of
nonvolatile memory.
In-system operation of the FM18L08 is very similar
to other RAM based devices. Read cycle and write
cycle times are equal. The FRAM memory, however,
is nonvolatile due to its unique ferroelectric memory
process. Unlike BBSRAM, the FM18L08 is a truly
monolithic nonvolatile memory. It provides the same
functional benefits of a fast write without the
disadvantages associated with modules and batteries
or hybrid memory solutions.
These capabilities make the FM18L08 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in a bytewide environment. The
availability of a surface-mount package improves the
manufacturability of new designs, while the DIP
package facilitates simple design retrofits. Device
specifications are guaranteed over a temperature
range of -40°C to +85°C.
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Industry Standard Configuration
•
Industrial Temperature -40° C to +85° C
•
32-pin “Green” TSOP Package
•
28-pin SOIC or DIP Package
•
“Green” Packaging Options
Pin Configurations
NC
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP-I
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
NC
Ordering Information
FM18L08-70-TG * 70 ns access, 32-pin “Green” TSOP
FM18L08-70-S *
70 ns access, 28-pin SOIC
FM18L08-70-P *
70 ns access, 28-pin DIP
FM18L08-70-SG * 70 ns access, 28-pin “Green” SOIC
FM18L08-70-PG * 70 ns access, 28-pin “Green” DIP
* End of life. Last time buy Nov. 2009.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
http://www.ramtron.com
Rev. 3.5
Sept. 2009
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FM18L08
A10-A14
Block Decoder
A0-A14
Address
Latch
A0-A7
Row
Decoder
32,768 x 8 FRAM Array
CE
Pin Description
Pin Name
A0-A14
DQ0-7
/CE
/OE
/WE
VDD
VSS
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A8-A9
Column Decoder
WE
OE
Control
Logic
I/O Latch
Bus Driver
DQ0-7
Figure 1. Block Diagram
Type
Input
I/O
Input
Input
Input
Supply
Supply
Pin Description
Address: The 15 address lines select one of 32,768 bytes in the FRAM array. The
address value is latched on the falling edge of /CE.
Data: 8-bit bi-directional data bus for accessing the FRAM array.
Chip Enable. /CE selects the device when low. Asserting /CE low causes the address
to be latched internally. Address changes that occur after /CE goes low will be
ignored until the next falling edge occurs.
Output Enable: Asserting /OE low causes the FM18L08 to drive the data bus when
valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.
Write Enable: Asserting /WE low causes the FM18L08 to write the contents of the
data bus to the address location latched by the falling edge of /CE.
Supply Voltage
Ground
Functional Truth Table
/CE
/WE
H
X
X
↓
L
H
L
↓
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
Write
Note: The /OE pin controls only the DQ output buffers.
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FM18L08
Overview
The FM18L08 is a bytewide FRAM memory. The
memory array is logically organized as 32,768 x 8
and is accessed using an industry standard parallel
interface. All data written to the part is immediately
nonvolatile with no delay. Functional operation of the
FRAM memory is the same as SRAM type devices,
except the FM18L08 requires a falling edge of /CE to
start each memory cycle.
The FM18L08 drives the data bus when /OE is
asserted to a low state. If /OE is asserted after the
memory access time has been satisfied, the data bus
will be driven with valid data. If /OE is asserted prior
to completion of the memory access, the data bus will
be driven when valid data is available. This feature
minimizes supply current in the system by eliminating
transients caused by invalid data being driven onto
the bus. When /OE is inactive the data bus will
remain tri-stated.
Write Operation
Writes operations require the same time as reads. The
FM18L08 supports both /CE- and /WE-controlled
write cycles. In all cases, the address is latched on the
falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM18L08 will not
drive the data bus regardless of the state of /OE.
In a /WE-controlled write, the memory cycle begins
on the falling edge of /CE. The /WE signal falls after
the falling edge of /CE. Therefore, the memory cycle
begins as a read. The data bus will be driven
according to the state of /OE until /WE falls. The
timing of both /CE- and /WE-controlled write cycles
is shown in the electrical specifications.
Write access to the array begins asynchronously after
the memory cycle is initiated. The write access
terminates on the rising edge of /WE or /CE,
whichever is first. Data set-up time, as shown in the
electrical specifications, indicates the interval during
which data cannot change prior to the end of the write
access.
Unlike other truly nonvolatile memory technologies,
there is no write delay with FRAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Therefore, any operation including read or
write can occur immediately following a write. Data
polling, a technique used with EEPROMs to
determine if a write is complete, is unnecessary.
Precharge Operation
The precharge operation is an internal condition
where the state of the memory is prepared for a new
access. All memory cycles consist of a memory
access and a precharge. The precharge is user
initiated by taking the /CE signal high or inactive. It
Memory Operation
Users access 32,768 memory locations each with 8
data bits through a parallel interface. The cycle time
is the same for read and write memory operations.
This simplifies memory controller logic and timing
circuits. Likewise the access time is the same for read
and write memory operations. When /CE is
deasserted high, a precharge operation begins, and is
required of every memory cycle. Thus unlike SRAM,
the access and cycle times are not equal. Writes occur
immediately at the end of the access with no delay.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed.
Note that the FM18L08 contains a limited low
voltage write protection circuit. This will prevent
access when V
DD
is much lower than the specified
operating range. It is still the user’s responsibility to
ensure that V
DD
is within data sheet tolerances to
prevent incorrect operation.
The FM18L08 is designed to operate in a manner
similar to other bytewide memory products. For users
familiar with SRAM, the performance is comparable
but the bytewide interface operates in a slightly
different manner as described below. For users
familiar with EEPROM, the obvious differences
result from the higher write performance of FRAM
technology including NoDelay writes and from
unlimited write endurance.
Read Operation
A read operation begins on the falling edge of /CE.
At this time, the address bits are latched and a
memory cycle is initiated. Once started, a full
memory cycle must be completed internally
regardless of the state of /CE. Data becomes available
on the bus after the access time has been satisfied.
After the address has been latched, the address value
may be changed upon satisfying the hold time
parameter. Unlike an SRAM, changing address values
will have no effect on the memory operation after the
address is latched.
Rev. 3.5
Sept. 2009
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FM18L08
must remain high for at least the minimum precharge
timing specification.
The user dictates the beginning of this operation since
a precharge will not begin until /CE rises. However,
the device has a maximum /CE low time specification
that must be satisfied.
FRAM Design Considerations
When designing with FRAM for the first time, users
of SRAM will recognize a few minor differences.
First, bytewide FRAM memories latch each address
on the falling edge of chip enable. This allows the
address bus to change after starting the memory
access. Since every access latches the memory
address on the falling edge of /CE, users cannot
ground it as they might with SRAM.
Users who are modifying existing designs to use
FRAM should examine the memory controller for
timing compatibility of address and control pins.
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change required. An example of the signal
relationships is shown in Figure 2 below. Also shown
is a common SRAM signal relationship that will not
work for the FM18L08.
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
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Valid Memory Signaling Relationship
CE
FRAM
signaling
Address
Data
Address 1
Address 2
Data 1
Data 2
Invalid Memory Signaling Relationship
CE
SRAM
signaling
Address
Data
Address 1
Address 2
Data 1
Data 2
Figure 2. Memory Address Relationships
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FM18L08
A second design consideration relates to the level of
V
DD
during operation. Battery-backed SRAMs are
forced to monitor V
DD
in order to switch to battery
backup. They typically block user access below a
certain V
DD
level in order to prevent loading the
battery with current demand from an active SRAM.
The user can be abruptly cut off from access to the
memory in a power down situation without warning.
FRAM memories do not need this system overhead.
The memory will not block access at any V
DD
level.
The user, however, should prevent the processor from
accessing memory when V
DD
is out-of-tolerance. The
common design practice of holding a processor in
reset during powerdown may be sufficient. It is
recommended that Chip Enable is pulled high and
allowed to track V
DD
during powerup and powerdown
cycles. It is the user’s responsibility to ensure that
chip enable is high to prevent accesses below V
DD
min. (3.0V). Figure 3 shows an external pullup
resistor on /CE which will keep the pin high during
power cycles assuming the MCU/MPU pin tri-states
during the reset condition. The pullup resistor value
should be chosen to ensure the /CE pin tracks V
DD
yet
a high enough value that the current drawn when /CE
is low is not an issue.
V
DD
R
FM18L08
CE
MCU/
MPU
WE
OE
A(14:0)
DQ
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Figure 3. Use of Pullup Resistor on /CE
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