IMAGE SENSORS
FT 18
Frame Transfer CCD Image Sensor
Product specification
File under Image Sensors
2000 January 7
Philips
Semiconductors
TRAD
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FT 18
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2/3-inch optical format
1M active pixels (1024H x 1024V)
Progressive scan
Excellent anti-blooming
Variable electronic shuttering
Square pixel structure
Hor. and Vert. binning
100% optical fill factor
High dynamic range (>60dB)
High sensitivity
Low dark current and fixed pattern noise
Low read-out noise
Data rate up to 40 MHz
Frame rate up to 30 Hz
Mirrored read-out option
Description
The FT 18 is a monochrome progressive-scan frame-transfer image
sensor offering 1K x 1K pixels at 30 frames per second through a
single output buffer. The combination of high speed and a high linear
dynamic range (>10 true bits at room temperature without cooling)
makes this device the perfect solution for high-end real time medical
X-ray, scientific and industrial applications. A second output can be
used for mirrored images. The device structure is shown in figure 1.
Device structure
Optical size:
Chip size:
Pixel size:
Active pixels:
Total no. of pixels:
Optical black pixels:
Timing pixels:
Dummy register cells:
Contour lines:
Optical black lines:
7.68 mm (H) x 7.68 mm (V)
8.9 mm (H) x 17.0 mm (V)
7.5 µm x 7.5 µm
1024 (H) x 1024 (V)
1072 (H) x 1048 (V)
Left: 20
Right: 20
Left: 4
Right: 4
Left: 7
Right: 7
Bottom: 1
Top: 4
Bottom: 11
Top: 8
8 black lines
4 contour
8 black line
lines
s
Image
Section
1024
active
lines
20
pix
20
1024 active pixels
pix
4
1 contour line
11 black lines
2096
lines
Storage
Section
Output 7
amplifier
1072 cells
Output register
7
Figure 1 - Device structure
2000 January
2
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FT 18
Architecture of the FT 18
The FT18 consists of a shielded storage section and an open image
section. Both sections have the same structure with identical cells
and properties. The only difference between the two sections is the
optical light shield.
The optical centres of all pixels in the image section form a square
grid. The charge is generated and integrated in this section. The
image section is controlled by four image clocks (A1 to A4). After
integration, the image charge is completely shifted to the storage
section. The integration time is electronically controlled by charge
reset (CR).
The storage section is controlled by four storage clocks (B1 to B4).
An output register is located below the storage section for read-out.
The output register has buffers at both ends. This allows either normal
or mirrored read-out.
Transport of the pixels in the output register is controlled by three
register clock phases (C1 to C3). The register can be used for vertical
binning. Horizontal binning can be achieved by summing pixel
charges under the floating diffusion. More information can be found
in the application note. Figure 2 shows the detailed internal structure.
IMAGE SECTION
Image diagonal
Aspect ratio
Active image width x height
Total width x height
Pixel width x height
Geometric fill factor
Image clock pins
Capacity of each clock phase
Number of active lines
Number of contour lines
Number of black lines
Total number of lines
Number of active pixels per line
Number of overscan (timing) pixels per line
Number of black reference pixels per line
Total number of pixels per line
10.9 mm
1:1
7.680 x 7.680 mm
2
8.040 x 7.860 mm
2
7.5 x 7.5 µm
2
100%
A1, A2, A3, A4
<3.75nF per pin
1024
4 (top) + 1 (bottom)
8 (top) + 11 (bottom)
1048
1024
8 (2x4)
40 (2x20)
1072
Storage width x height
Cell width x height
Storage clock phases
Capacity of each B phase
Number of cells per line x number of lines
STORAGE SECTION
8.040 x 7.860 mm
2
7.5 x 7.5 µm
2
B1, B2, B3, B4
<4.1nF per pin
1072 x 1048
OUTPUT REGISTER
Output buffers (three-stage source follower)
Number of registers
Number of register cells below storage
Number of extra cells to output
Output register horizontal transport clock pins
Capacity of each C-clock phase
Overlap capacity between neighbouring C-clocks
Reset Gate clock phases
Capacity of each RG
2
1 (bidirectional below storage)
1072
2x7
3 (C1..C3)
<85pF per pin
<35pF
2 pins (RGL, RGR)
<15pF
2000 January
3
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FT 18
A2
A3
A4
A1
A2
A3
A4
A1
12 lines
A2
A3
A4
A1
A2
A2
A3
A4
A1
A2
A3
A4
One Pixel
A3
A4
A1
A2
A3
A4
A1
A2
A3
A4
A1
1K active
images
lines
IMAGE
A1
A2
A3
A4
A1
A2
A3
A4
A1
A2
A3
A4
A1
B2
B3
B4
B1
12 lines
FT CCD
A2
A3
A4
A1
B2
B3
B4
B1
B2
A1
B3
B4
B1
B2
B3
B4
B1
B2
A1
B3
B4
B1
B2
B3
B4
B1
STORAGE
1048 storage lines
B2
A1
B3
B4
B1
B2
B3
B4
B3
B2
A1
B3
B4
B1
B2
B3
B4
B3
B2
A1
B3
B4
B1
C2 C1
C3
C2
C1
C3
C2 C1
C3
C2
C1
C3
C2
C1
C3
C2
C1
C3
C2
C1
C3
C2
C1
C3
C2
C1
C3
B2
A1
B3
B4
B1
C2 C1
C3
C2
C1
C3
C2
C1
C3
OUTL
OG
C3
OUTR
OG
column
1
7 extra cells
20 black & 4 timing columns
column
24+1
column
24+1K
column
24+1K+24
4 timing & 20 black columns
7 extra cells
1K image pixels
A1, A2, A3, A4: clocks of image section
B1, B2, B3, B4: clocks of storage section
C1, C2, C3: clocks of horizontal register
OG: output gate
Figure 2 - Detailed internal structure
2000 January
4
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FT 18
Specifications
Absolute Maximum Ratings
GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock (absolute value)
OUT current (no short circuit protections)
VOLTAGES IN RELATION TO VNS:
VPS, SFS
SFD
RD
All other pins
VOLTAGES IN RELATION TO VPS:
VNS
SFD, RD
SFS
All other pins
DC Conditions
1
VNS
2
VPS
SFD
SFS
VCS
OG
RD
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
Min.
Max.
Unit
-55
-40
-20
-0.2
0
+80
+60
+20
+0.2
6
°C
°C
V
µA
mA
-30
-8
-15
-32
-0.5
+0
-8
-20
Min.
16
2
18
-
-2
3
12
+0.5
+8
+0.5
+0.5
+30
+30
+8
+20
Typical
adjusted
4
20
0
0
5.4
13
Max.
24
6
22
-
3
8
15
V
V
V
V
V
V
V
V
Unit
V
V
V
V
V
V
V
AC Clock Level Conditions
1
IMAGE CLOCKS:
A-clock swing
A-clock low level
Charge Reset (CR) level on A-clocks
3
Charge Pump (CP) level on A- clocks
STORAGE CLOCKS (duty cycle=5/8):
B-clock swing
B-clock low level
OUTPUT REGISTER CLOCKS (duty cycle=1/2):
C-clock swing
C-clock low level
OTHER CLOCKS:
Reset Gate (RG) swing
Reset Gate (RG) low level
1
2
Min.
Typical
Max.
Unit
9.5
-
-
-
9.5
-
-
-
10
0
-5
0
10
0
5
3
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
-
-
10
1
12
-
V
V
All voltages in relation to SFS.
To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.
3
Guaranteed charge reset requires the CR voltage to last at least 1.2µs.
2000 January
5
