FX802
DVSR C
ODEC
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
CS
IRQ
XTAL/
CLOCK
XTAL
AUDIO
IN
AUDIO
BYPASS
AUDIO
OUT
C-BUS INTERFACE AND CONTROL LOGIC
CLOCK
GENERATOR
DECODER
OUTPUT
V
BIAS
CONTROL
PLAY
COMMAND
BUFFER
STORE
COMMAND
BUFFER
REGISTER
STATUS
REGISTER
ENCODE
CLOCK
DECODE
CLOCK
DATA
READ
COUNTER
DATA
WRITE
COUNTER
SPEECH
PLAY
COUNTERS
SPEECH
STORE
COUNTERS
ENCODER
CLOCK
DECODER
CLOCK
POWER
ASSESS
MOD
DEMOD
IDLE
PATTERN
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS and DATA
WE
CAS
RAS 1 RAS 2 RAS 3 RAS 4
A9
A8
A7
A6
A5
A4
A3/ECK
A2/DCK
A0/ENO
(ENCODER
OUT)
A1/ DEI
(DECODER
IN)
V
DD
DRAM ADDRESS LINES
V
BIAS
V
SS
Fig.1 FX802 DVSR Codec
Brief Description
The FX802 DVSR Codec contains:
A Continuously Variable Slope Delta Modulation (CVSD)
encoder and decoder.
Control and timing circuitry for up to 4Mbits of external
Dynamic Random Access Memory (DRAM).
“C-BUS”
µProcessor
interface and control logic.
When used with external DRAM, the FX802 has four primary
functions:
q
Speech Storage
Speech signals present at the Audio Input may be digitized
by the CVSD encoder, and the resulting bit stream stored
in DRAM. This process also provides readings of input
power level for use by the system
µController.
q
Speech Playback
Previously digitized speech data may be read from DRAM
and converted back into analogue form by the CVSD
decoder.
q
Data Storage
Digital data sent over the “C-BUS” from the system
µController
may be stored in DRAM.
q
Data Retrieval
Digital data may be read from DRAM and sent over
“C-BUS” to the system
µController.
Speech storage and playback may be performed
concurrently with data storage or retrieval.
The FX802 may also be used without DRAM (as a “stand-
alone” CVSD Codec), in which case direct access is
provided to the CVSD Codec digital data and clock signals.
All functions are controlled by “C-BUS” commands from
the system
µController.
The Storage, Recovery and Replay functions of the
FX802 can be used for:
q
Answering Machine applications, where an incoming
speech message is stored for later recall.
q
Busy Buffering, an outgoing speech message is stored
temporarily until the transmit channel becomes free.
q
Automatic transmission of pre-recorded ‘Alarm’ or
status announcements.
q
Time Domain Scrambling of speech messages.
q
VOX control of transmitter functions.
q
Temporary Data Storage applications, such as
buffering of over-air data transmissions.
On-chip the Delta Codec is supported by input and output
analogue switched-capacitor filters and audio output
switching circuitry. The DRAM control and timing circuitry
provides all the necessary address, control and refresh
signals to interface to external DRAM.
The FX802 DVSR Codec is a low-power 5-volt CMOS LSI
device.
Publication D/802/4 December 1995
Pin Number Function
FX802
J
1
FX802
LG/LS
Row Address Strobe 2 (RAS2):
Should be connected to the Row Address Strobe input of the second
1Mbit DRAM chip (if fitted).
2
1
Row Address Strobe 1 (RAS1):
Should be connected to the Row Address Strobe input of the first
DRAM chip.
3
2
Write Enable (WE):
The DRAM Read/Write control pin.
4
Xtal:
The output of the on-chip clock oscillator. External components are required at this output when
a Xtal is employed. A Xtal cannot be used with the 24-pin version.
5
3
Xtal/Clock:
The input to the on-chip clock oscillator inverter. A 4.0MHz Xtal or externally derived clock
should be connected here, see Figure 2. This clock provides timing for on-chip elements, filters etc. A
Xtal cannot be used with the 24-pin version. Various Xtal frequencies can be used with this device, see
Table 3 for the sampling clock rate variations.
Interrupt Request (IRQ):
The output of this pin indicates an interrupt condition to the
µController,
by
going to a logic “0.” This is a “wire-or able” output, enabling the connection of up to 8 peripherals to 1
interrupt port on the
µController.
The pin has a low-impedance pulldown to logic “0” when active and a
high impedance when inactive.
Conditions indicated by this function are:
Power Reading Ready, Play Command Complete, Store Command Complete.
Serial Clock:
The “C-BUS,” serial clock input. This clock, produced by the
µController,
is used for
transfer timing of commands and data to and from the DVSR Codec. See Timing Diagrams and
System Support Document, Document 2. The clock-rate requirements vary for differing FX802
functions.
Command Data:
The “C-BUS,” serial data input from the
µController.
Data is loaded to this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams
and System Support Document, Document 2.
6
4
7
5
8
6
9
7
Chip Select (CS):
The “C-BUS”, data transfer control function, this input is provided by the
µController.
Command Data transfer sequences are initiated, completed or aborted by the CS signal.
See Timing Diagrams and System Support Document, Document 2.
Reply Data:
The “C-BUS,” serial data output to the
µController.
The transmission of Reply Data bytes
is synchronized to the Serial Data Clock under the control of the Chip Select input. This 3-state output
is held at high impedance when not sending data to the
µController.
See Timing Diagrams and System
Support Document, Document 2.
10
8
11
9
V
BIAS
:
The output of the on-chip analogue circuitry bias system, held internally at V
DD
/2. This pin should
be decoupled to V
SS
by a capacitor C
1
, See Figure 2.
Audio Out:
The analogue signal output.
12
10
13
11
Audio In:
The audio (speech) input. The signal to this pin must be a.c. coupled by a capacitor C
4
and
decoupled to V
SS
by an HF bypass capacitor C
6
. For optimum noise performance this input should be
driven from a source impedance of less than 100Ω.
14
12
V
SS
:
Negative supply rail (GND).
2
Pin Number Function
FX802
J
15
FX802
LG/LS
13
DRAM Data In/A0/ (Direct Access – Encoder Out (ENO)):
Connected to the DRAM data input and
address line A0. With no DRAM employed this output is available (in Direct Access mode) as the Delta
Encoder digital data output. Direct Access control is achieved by Control Register byte 1 – bit 6.
16
14
DRAM Data Out/ A1/ (Direct Access – Decoder In (DEI)):
Connected to the DRAM data output and
address line A1. With no DRAM employed this pin is available (in Direct Access mode) as the Delta
Decoder digital data input. Direct Access control is achieved by Control Register byte 1 – bit 6.
17
15
DRAM A2/ (Direct Access – Decoder Clock (DCK)):
DRAM address line A2. With no DRAM
employed this pin is available (in Direct Access mode) as the Delta Decoder Clock input. Direct Access
control is achieved by Control Register byte 1 – bit 6.
18
16
DRAM A3/ (Direct Access – Encoder Clock (ECK)):
DRAM address line A3. With no DRAM
employed this pin is available (in Direct Access mode) as the Delta Encoder Clock output. Direct
Access control is achieved by Control Register byte 1 – bit 6.
19
17
DRAM A4:
DRAM address line A4.
20
18
DRAM A5:
DRAM address line A5.
21
19
DRAM A6:
DRAM address line A6.
22
20
DRAM A7:
DRAM address line A7.
23
21
DRAM A8:
DRAM address line A8.
24
Row Address Strobe 4 (RAS4):
Should be connected to the Row Address Strobe input of the fourth
1Mbit DRAM chip (if fitted).
25
Row Address Strobe 3 (RAS3):
Should be connected to the Row Address Strobe input of the third
1Mbit DRAM chip (if fitted).
26
22
DRAM A9:
DRAM address line A9. This pin is not connected when a 256kbit DRAM is employed.
Note:
To simplify PCB layout, the DRAM address inputs A0 – A8 may be connected in any physical
order to the DVSR Codec output pins A0 – A8.
27
23
Column Address Strobe (CAS):
The DRAM Column Address Strobe pin. Should be connected to the
CAS pins of all DRAM chips.
28
24
V
DD
: Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the
DVSR Codec are dependant upon this supply.
3
External Components
V
DD
C
5
4 x 1Mbit
DRAM
A0 – A9
WE
CAS
RAS
D
Q
V
SS
RAS2
R
1
1 §
2
3
4 §
5
6
7
8
9
10
11
12
13
14
V
DD
28
27
26
§ 25
§ 24
23
22
CAS
A9
RAS3
RAS4
A8
A7
A6
A5
A4
A3/ECK
A2/DCK
A1/DEI
A0/ENO
RAS1
WE
XTAL
See INSET
XTAL/CLOCK
IRQ
SERIAL CLOCK
A0 – A9
WE
CAS
RAS
D
Q
C-BUS
INTERFACE
COMMAND DATA
CS
REPLY DATA
V
BIAS
AUDIO OUT
AUDIO IN
C
4
C
6
V
SS
FX802J
21
20
19
18
17
16
15
A0 – A9
WE
CAS
RAS
D
Q
C
1
R
3
V
SS
A0 – A9
WE
CAS
RAS
D
Q
INSET
XTAL
Component
4§
Value
22.0kΩ
1.0MΩ
1.0kΩ
1.0µF
33.0pF
33.0pF
C
4
C
5
C
6
X
1
=
1.0µF
1.0µF
1.0nF
4.00MHz
4.032MHz
4.096MHz
X
1
R
2
FX802J
XTAL/CLOCK
C
3
C
2
V
SS
5
R
1
R
2
R
3
C
1
C
2
C
3
=
or
or
Tolerance: R =
±10%
C =
±20%
Fig.2 Recommended Component and DRAM Connections
Notes
1. Xtal circuitry shown INSET is in accordance with CML
Application Note D/XT/2 December 1991.
2. External Xtal circuitry is not applicable to the 24-pin/lead
versions of this device, only a clock pulse input can be
used.
3. Functions whose pins are marked § above are not
available on the 24-pin/lead versions of this device. Pin
numbers illustrated are for 28-pin versions.
4. Table 3 details the actual encoder/decoder sample rates
available using the Xtal frequencies recommended above.
5. R
1
is used as the DBS 800 system common-pullup for the
“C-BUS” Interrupt Request (IRQ) line, the optimum value
will depend upon the circuitry connected to the IRQ line.
Up to 8 peripherals may be connected to this line.
6. Recommended DRAM Parameters:
256kbit x 1 or 1Mbit x 1 Dynamic Random Access Memory
with ‘CAS before RAS’ refresh mode, maximum Row
Address Access time = 200nsec.
Example DRAM types:
256kbit (262,144bits)
Texas Instruments
Hitachi
1Mbit (1,048,576bits)
Texas Instruments
Hitachi
TMS4256–20
HM51256–15
TMX4C1024–15
HM511000–15
7. Figure 2 (above) shows connections to 4 x 1Mbit sections
of DRAM. If desired, to simplify PCB layout, the DRAM
inputs A0 to A8 may be connected in any order to the
FX802 DVSR Codec output pins A0 to A8. Connections to
256kbit DRAM are similar, but A9 unconnected.
8. When using the FX802 “stand-alone (Direct Access),” no
DRAM should be connected.
4
Controlling Protocol
Control of the functions of the FX802 DVSR Codec is by a group of Address/Commands (A/Cs) and appended instructions or
data to and from the system
µController
(see Figure 5). The use and content of these instructions is detailed in the following
paragraphs and tables.
Command
Assignment
General Reset
Write to Control Register
Read Status Register
Store ‘N’ pages. Start page ‘X’
Store ‘N’ pages. Start page ‘X’
Play ‘N’ pages. Start page ‘X’
Play ‘N’ pages. Start page ‘X’
Write Data. Start page ‘P’
Read Data. Start page ‘P’
Write Data – Continue
Read Data – Continue
Address/Command (A/C) Byte
Hex.
Binary
MSB
LSB
01
60
61
62
63
64
65
66
67
68
69
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
+
Data
Byte/s
+
+
+
+
+
+
+
+
+
+
2 byte Instruction to Control Register
1 byte Reply from Status Register
2 bytes Command – Immediate
2 bytes Command – Buffered
2 bytes Command – Immediate
2 bytes Command – Buffered
2 bytes ‘P’ + Write data
2 bytes ‘P’ + Read data
Write data
Read data
Table 1 “C-BUS” Address/Commands
Address/Commands
Instruction and data transactions to and from this device
consist of an Address/Command (A/C) byte followed by
either:
(i) a further instruction or data, or
(ii) a Status or data Reply.
Control and configuration is by writing instructions from the
µController
to the Control Register (60
H
).
Reporting of FX802 configurations is by reading the Status
Register (61
H
). Instructions and data are transferred, via
“C-BUS,” in accordance with the timing information given in
Figures 5 and 6.
A complete list of DBS 800 “C-BUS” Address locations is
published in the System Support Document.
Speech
The delta encoder and decoder sampling rates are
independently set, via the Control Register (Table 4), to
(nominally) 16, 25, 32, 50 or 64kbits/s (see Tables 2 and 3),
allowing the user to choose between speech-quality and
storage-time, whilst providing for time-compression or
expansion of the speech signals.
The DVSR Codec can handle from 256kbits to 4Mbits of
DRAM, giving, in the case of 32kbit/s sampling rate, from 8
to 131 seconds of speech storage.
For speech storage purposes, the memory is divided into
'pages' of 1024 bits each, corresponding to 32ms at a
32kbit/s sampling rate.
A 256kbit DRAM contains
256 pages.
A 1Mbit DRAM contains
1024 pages.
4Mbit of DRAM contains
4096 pages.
The Delta Codec may be used without DRAM, when the
decoder sampling rate (8 to 64 kbits/s) is determined by an
external clock source applied to the Decoder Clock pin.
Operation with DRAM
The FX802 can operate with up to 4Mbits of DRAM. When
used with DRAM the DVSR Codec performs four main
functions under the control of commands received over the
“C-BUS” interface from the
µController:
Stores Speech
by digitally encoding the analogue input
signal and writing the resulting digital data into the
associated Dynamic RAM (DRAM).
Plays
stored speech by reading the digital data stored in the
DRAM and decoding it to provide an analogue output
signal.
Writes
data sent over the “C-BUS” from the
µController
to
DRAM.
Reads
data from DRAM, sending it to the
µC
over the
“C-BUS”.
‘Data’ is directed to and from DRAM by the on-chip DRAM
Controller.
Store and Play Speech Commands
Speech storage and playback may take place
simultaneously.
These commands are transmitted, via “C-BUS,” to the
FX802, in the form:
STORE or PLAY ‘N’ (1024-bit) pages (of encoded
speech data) starting at page ‘X.’
‘N’
is any number from 1 to 16 (pages) and
‘X’
from (page) 0
to 4095 (4Mbit DRAM), as illustrated below.
Preceded by the A/C, this command writes 16-bits (byte 1
(first) and byte 0) of data from the
µC
to the FX802 Store or
Play Command Buffer.
MSB
Byte 1
Byte 0
LSB
15 14 13 12 11 10 9
‘N’
5
8
7
6
5
‘X’
4
3
2
1
0
模拟电子
