G -LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
Features :
∗
∗
∗
∗
∗
65,536 words by 16 bits organization.
Fast access time and cycle time.
Dual CAS Input.
Low power dissipation.
Read-Modify-Write, RAS -Only Refresh,
Description :
The GLT41016 is a 65,536 x 16 bit high-
performance CMOS dynamic random access
memory. The GLT41016 offers Fast Page
mode with Extended Data Output, and has
both BYTE WRITE and WORD WRITE
access cycles via two CAS pins. The
GLT41016 accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 256 x 16 bits, within a page, with cycle
times as short as 12ns.
The GLT41016 is best suited for
graphics, and DSP applications requiring
high performance memories.
CAS -Before- RAS Refresh, Hidden
Refresh and Test Mode Capability.
∗
256 refresh cycles per 4ms.
∗
Available in 40-pin 400 mil SOJ and 40/44
pin TSOP (II).
∗
Single 5.0V±10% Power Supply.
∗
All inputs and Outputs are TTL
compatible.
∗
Extended Data-Out(EDO) Page Mode
operation.
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
AA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
Max. CAS Access Time (t
CAC
)
30
30 ns
15 ns
12 ns
65 ns
10 ns
35
35 ns
18 ns
13 ns
70 ns
11 ns
40
40 ns
20 ns
15 ns
75 ns
12 ns
45
45 ns
22 ns
18 ns
80 ns
12 ns
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-1-
G -LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
Pin Configuration :
GLT41016
SOJ Top View
TSOP(Type II)
Top View
Pin Descriptions:
Name
A
0
- A
7
RAS
UCAS
LCAS
WE
OE
DQ
0
- DQ
15
V
CC
V
SS
NC
Function
Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Inputs / Outputs
+5V Power Supply
Ground
No Connection
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-2-
G -LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
Absolute Maximum Ratings*
Operating Temperature, T
A
(ambient)
Capacitance*
T
A
=25°C, V
CC
=5V±10%, V
SS
=0V
Unit
pF
pF
pF
Max.
Parameter
Symbol
.......................................-0°C to +70°C
5
Address Input
Storage Temperature(plastic)....-55°C to +150°C C
IN1
Voltage Relative to V
SS
...............-1.0V to + 7.0V C
IN2
7
RAS , LCAS , UCAS , WE , OE
Short Circuit Output Current......................50mA
7
Data Input/ Output
Power Dissipation......................................1.0W C
OUT
*Note: Operation above Absolute Maximum Ratings *Note: Capacitance is sampled and not 100% tested
can adversely affect device reliability.
Electrical Specifications
l
l
l
CAS means UCAS and LCAS .
All voltages are referenced to GND.
After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-3-
G -LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
Extended Data Output (EDO) Page Mode
The EDO page mode is a kind of page mode with enhanced features. The two major features
of the EDO page mode are as follows.
1. Data output time is extended.
In the EDO page mode, the output data is held to the next CAS cycle‘s falling edge,
instead of the rising edge. For this reason, valid data output time in the EDO page mode is
extended compared with the fast page mode (=data extend function). In the fast page mode,
the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in
the EDO page mode, the timing margin in read cycle is larger than of the fast page mode
even if the CAS cycle time becomes shorter.
2. The CAS cycle time in the EDO page mode is shorter than that in the fast page mode.
In the EDO page mode, due to the data extend function, the CAS cycle time can be
shorter than in the fast page mode if the timing margin is the same.
Taking a device whose t
RAC
is 60ns as an example, the CAS cycle time in the EDO page
mode is 25ns while that in the fast page mode is 40ns.
In the EDO page mode, read (data out) and write (data in) cycles can be executed
repeatedly during one RAS cycle. The EDO page mode allows both read and write
operations during one cycle, but the performance is equivalent to that of the fast page mode
in that case.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-4-
G -LINK
GLT41016
64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Dec 1998 (Rev 2.1)
Truth Table: GLT41016
Function
Standby
Read: Word
Read: Lower Byte
RAS
H
L
L
CASL CASH
H→X H→X
L
L
L
H
WE
X
H
H
OE
X
L
L
ADDRESS
High-Z
DQs
Notes
ROW/COL Data Out
ROW/COL Lower Byte,Data-
Out
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-
Out
ROW/COL Data-In
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
ROW/COL Data-Out,Data-In
ROW/COL Data-Out
COL
Data-Out
Read: Upper Byte
L
H
L
H
L
Write: Word(Early Write)
Write: Lower Byte (Early)
Write: Upper Byte (Early)
Read Write
EDO-Page-
Mode Read
EDO-Page-
Mode Write
EDO-Page-
Mode Read-
Write
Hidden
Refresh
2nd Cycle
Read
Write
RAS -Only Refresh
CBR Refresh
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
L
L
L
L
L
L
L
L
L
L
L
H
L
H→L
H→L
H→L
H→L
H→L
L
H
L
L
H→L
H→L
H→L
H→L
H→L
L
L
L
H→L
H
H
L
L
H→L
X
X
X
L→H
L
L
X
X
L→H
1,2
1
1
2
2
1,2
ROW/COL Data-In
COL
Data-In
ROW/COL Data-Out,Data-In
L
L→H→L
L→H→L
L
H→L
H→L
L
L
H
L
H→L
L
L
H
L
H→L
H
L
X
X
L→H
L
X
X
X
COL
Data-Out,Data-In
1,2
1
2,3
ROW/COL Data-Out
ROW/COL Data-In
ROW
High-Z
High-Z
4
Notes:
1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active).
2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active ( UCAS or LCAS ).
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
-5-
