Preliminary
GS8170S18/36/72B-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb
Σ
1x1 MultiMode SRAM
1M x 18, 512K x 36, 256K x 72
250 - 333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• User-configurable Early, Late and Double Late Write mode
• User-configurable pipelined and flow through operation
• JEDEC standard SigmaRAM
™
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Dual Cycle Deselect in Pipeline mode
• Burst Synchronous operation
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers in Pipeline
mode
• ZQ mode pin for user-selectable output drive strength
• Byte write operation (9-bit bytes)
• 2 User programmable chip enable inputs for easy depth
expansion.
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin compatible with future 32M, 64M, and 128M devices
- 333
3.0 ns
1.5 ns
5 ns
5 ns
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Pipeline mode
Flow Through mode
tKHKH
tKHQV
tKHKH
tKHQV
Functional Description
Because SigmaRAMs are synchronous devices, address, data
inputs, and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
A
ΣRAM
may be configured by the user to read in Pipeline or
Flow Through mode. In Pipeline mode, single data rate
ΣRAMs
incorporate a rising-edge-triggered output register.
For read cycles, a pipelined SRAM’s output data is staged at
the input of an edge-triggered output register during the access
cycle and then released to the output drivers at the next rising
edge of clock.
GS817x18/36/72B
ΣRAMs
are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
SigmaRAM Family Overview
GS8170S18/36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage CMOS I/O SRAMs
designed to operate at the speeds needed to implement
economical high performance networking systems.
GSI's
ΣRAMs
are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
ΣRAM
™
family standard allows a user to implement the
interface protocol best suited to the task at hand.
Rev: 1.04b 06/2001
1/45
© 2001, GSI Technology, Inc.
D
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170S18/36/72B-333/300/250
8170S72B 256K x 72 Pinout
256K x 72 Common I/O—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2001.03
2
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
3
A
Bc
Bh
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
Bg
Bd
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
(16M)
NC
NC
(128M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
V
DD
MCL
A
A1
A0
7
A
(8M)
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
A
A
8
E3
Bb
Be
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
Bf
Ba
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 1.04b 06/2001
2/45
© 2001, GSI Technology, Inc.
D
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170S18/36/72B-333/300/250
8170S36B 512K x 36 Pinout
512K x 36 Common I/O—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2001.03
2
NC
NC
NC
NC
DQPc
DQc
DQc
DQc
DQc
CQ2
NC
NC
NC
NC
NC
DQd
DQd
DQd
DQd
3
A
Bc
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
NC
Bd
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
(16M)
A
NC
(128M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC (64M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
V
DD
MCL
A
A1
A0
7
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC (32M)
A
A
8
E3
Bb
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
NC
Ba
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
11
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQc
DQc
DQc
DQc
CQ2
NC
NC
NC
NC
DQPd
DQd
DQd
DQd
DQd
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 1.04b 06/2001
3/45
© 2001, GSI Technology, Inc.
D
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170S18/36/72B-333/300/250
8170S18 1M x 18 Pinout
1M x 18 Common I/O—Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2001.03
2
NC
NC
NC
NC
DQPb
DQb
DQb
DQb
DQb
CQ2
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
A
Bb
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
E2
NC
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
(16M)
A
NC
(128M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
V
DD
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
V
DD
MCL
A
A1
A0
7
A
A
A
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(32M)
A
A
8
E3
NC
NC
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
NC
Ba
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
NC
NC
NC
NC
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
CQ2
NC
NC
NC
NC
NC
NC
NC
NC
NC
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Rev: 1.04b 06/2001
4/45
© 2001, GSI Technology, Inc.
D
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170S18/36/72B-333/300/250
Pin Description Table
Pin Location
A3, A5, A7, A9, B7, U4,
U6, U8, V3, V4, V5, V6,
V7, V8, V9, W5, W6, W7
C7
B5
A6
B3, C9
B8, C4
B4, B9, C3, C8
K3
K1, K11
K2, K10
E2, F1, F2, G1, G2, H1,
H2, J1, J2, L10, L11,
M10, M11, N10, N11,
P10, P11, R10
A10, A11, B10, B11,
C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
A1, A2, B1, B2, C1, C2,
D1, D2, E1, E10, F10,
F11, G10, G11, H10,
H11, J10, J11, L1, L2,
M1, M2, N1, N2, P1, P2,
R2, R11, T10, T11, U10,
U11, V10, V11, W10,
W11
C6
A4, A8
G6, H6
W9
W4
W8
W3
L6, M6, J6
N6
Rev: 1.04b 06/2001
Symbol
A
A
A
ADV
Bx
Bx
Bx
CK
CQ
CQ
DQ
Description
Address
Address
Address
Advance
Byte Write Enable
Byte Write Enable
Byte Write Enable
Clock
Echo Clock
Echo Clock
Data I/O
Type
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input/Output
Comments
—
x18 version only
x18 and x36 versions
Active High
Active Low (all versions)
Active Low (x36 and x72 versions)
Active Low (x72 version only)
Active High
Active High
Active Low
x18, x36, and x72 versions
DQ
Data I/O
Input/Output
x36 and x72 versions
DQ
Data I/O
Input/Output
x72 version only
E1
E2 & E3
EP2 & EP3
TCK
TDI
TDO
TMS
M2, M3 & M4
SD
Chip Enable
Chip Enable
Chip Enable Program Pin
Test Clock
Test Data In
Test Data Out
Test Mode Select
Mode Control Pins
Slow Down
5/45
Input
Input
Input
Input
Input
Output
Input
Input
Input
Active Low
Programmable Active High or Low
—
Active High
—
—
—
—
Active Low
© 2001, GSI Technology, Inc.
D
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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