H25PL13S
Data Sheet
1. General Description
The H25PL13S is a 2.5V CMOS (0.25㎛ 1-poly, 3-metal) analog programmable frequency
synthesizer based on charged pump type PLL for an on-chip application using Hynix standard
0.25㎛ ASIC Process. H25PL13S has 5MHz to 320MHz output range. Operating frequency of
PLL is fully programmable.
2. Features
• On-chip charge pump type PLL clock generator
• Input reference clock range : 4MHz ~ 100MHz
• Clock output frequency range : 5MHz ~ 160MHz( extend to 320MHz )
• Reference divider range : 1 ~ 256 ( 8-bit programmable divider)
• Feedback divider range : 3 ~ 16386 ( 14-bit programmable divider)
• External loop filter only
• programmable VCO range and VCO gain( 2-bit )
• programmable PD gain ( 2-bit )
• Maximum Power consumption : 15mW
• Cell Size : 611㎛ x 454㎛
3. Block Diagram and Recommended Application Circuits
tpdud[1:0]
ncb[7:0]
icp[3:0]
vc[1:0]
vcopd
vcoinitt
bpck
tdm
p[1:0]
bypass
n[7:0]
DVDD
ref
cnttest
m[13:0]
14 BIT
COUNTER
m<13:0>+2
pd
reset
8 BIT
COUNTER
n<7:0>+1
PFD
CHARGE
PUMP
VCO
Analog part
pd
pd
Post
divider
p[1:0]+1
2
DVSS
ck
reset
pd
reset
AVDD
Lock
detector
AVSS
10uF
mc[13:0]
lfo
RLFE
CLF2E
lock
4.7nF
2.5V
ground
CLFE
AVDD
External loop filter is optional
If you use internal loop filter mode,
lfo
port
doesn’t need to be connected.
Separate AVDD, AVSS properly
from digital and system power and signal
: External pin of chip
ⓒ
2004 Hynix Semiconductor Inc. All rights reserved.
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H25PL13S
Data Sheet
4. Pin Descriptions
Pin Name
DVDD
DVSS
AVDD
AVSS
AVSS2
ref
bpck
pd
vcopd
bypass
tdm
reset
vcoinit
cnttest
tpdud[1:0]
m[13:0]
n[7:0]
p[1:0]
vc[1:0]
icp[3:0]
Type
Power
Ground
Power
Ground
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Digital power supply
Digital ground
Analog power supply
Analog ground
Guard ring ground
PLL reference clock input signal
Bypass clock input signal
PLL power down mode except VCO : active high
VCO power down mode : active high
Bypass mode : active high
Digital part test mode : active high
Digital part reset signal : active high
VCO initialize signal : active high
Counter toggle test : active high
Charge pump test mode( Normal mode : “00”)
Feedback divisor is M[13:0]+2
Reference divisor is N[7:0]+1
Post divisor is 2
P[1:0]+1
VCO range control vector
Charge pump bias current control vector
ⓒ
2004 Hynix Semiconductor Inc. All rights reserved.
2 / 17
H25PL13S
Data Sheet
Pin Name
lfo
ck
lock
ncb[7:0]
mc[13:0]
Type
Inout
Output
Output
Output
Output
Description
External loop filter port
PLL output clock
PLL lock detect signal : active high
Reference divider test output
Feedback divider test output
ⓒ
2004 Hynix Semiconductor Inc. All rights reserved.
3 / 17
H25PL13S
Data Sheet
5. Function Descriptions
H25PL13S is ideally suited to provide the graphics system clock signals required by
video signal AD and DA. Fully Programmable feedback and reference divider
capability allow virtually any frequency to be generated, not just simple multiples of
reference frequency. Also PD gain, VCO gain and VCO range are programmable
for user-define PLL characteristics.
(1) Determining Output Frequency
H25PL13S generates its output frequencies using charge pump PLL techniques.
Then The output frequency is ratiometrically related to the reference frequency.
a) Normal Frequency mode
Output frequency range : 5MHz ~ 160MHz
* PLL control setting
tdm = “low”, bypass = “low”
At this condition, the output frequency, F(ck), is actually determined by the following
equation.
F(ref)
.
(Feedback Divisor)
.
F(ck) =
(Reference Divisor)
F(ck) : frequency of output,
ck
F(ref) : frequency of reference pin,
ref
Feedback Divisor :
m[13:0]
+2
Reference Divisor :
n[9:0]
+1
* F(ck) range is showed section 3).
F(ref) range is restricted by loop filter mode at section 4).
ⓒ
2004 Hynix Semiconductor Inc. All rights reserved.
4 / 17
H25PL13S
Data Sheet
b) Extended Frequency mode
* PLL control setting
tdm = “low”, bypass = “high”
At this condition, the output frequency, F(ck), is actually determined by the following equation.
F(ref)
.
( Feedback Divisor)
.
(Post divisor)
(Reference Divider)
Pre divisor : 2
p[1:0]+1
Table. F(ck) range at extended frequency range
F(ck)
vc[1:0]
00
01
10
11
min
80MHz
120MHz
160MHz
200MHz
max
200MHz
240MHz
280MHz
320MHz
F(ck) =
(2) PD gain programming
H25PL13S provides various PD gain. Actually PD gain is controlled internally by
charge pump current. At charge pump PLL, PD gain is charge pump current over
2π. H25PL13S controls charge pump current by 4-bit resolution with the following
equations.
.
[A]
ICP = (ICPB/16)
.
(16 -
icp[3:0]
)
Kpd = ICP / 2π
[A/rad]
ICPB : Charge pump reference current. Typically 40uA
ICP : Charge pump current
Kpd : PD gain
ⓒ
2004 Hynix Semiconductor Inc. All rights reserved.
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