HB56UW865DB-5/5L/6/6L
64MB EDO DRAM S.O.DIMM
8-Mword
×
64-bit, 4k refresh, 1 Bank Module
(8 pcs of 8M
×
8 components)
ADE-203-862A (Z)
Rev. 1.0
May 15, 1998
Description
The HB56UW865DB Series is a 8 M
×
64 Dynamic RAM Small Outline Dual In-line Memory Module (S.
O. DIMM), mounted 8 pieces of 64-Mbit DRAM (HM5165805) sealed in TSOP package and 1 piece of
serial EEPROM for Presence Detect (PD). The HB56UW865DB Series offers Extended Data Out (EDO)
Page Mode as a high speed access mode. An outline of the HB56UW865DB Series is 144-pin Zig Zag
Dual tabs socket type compact and thin package. Therefore, the HB56UW865DB Series makes high
density mounting possible without surface mount technology. The HB56UW865DB Series provides
common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the its module
board.
Features
•
144-pin Zig Zag Dual tabs socket type
Outline: 67.60 mm (Length)
×
25.40 mm (Height)
×
3.80 mm (Thickness)
Lead pitch : 0.80 mm
•
Single 3.3 V supply: 3.3 V
±
0.3 V
•
High speed
Access time: t
RAC
= 50 ns/60 ns (max)
Access time: t
CAC
= 13 ns/15 ns (max)
•
Low power dissipation
Active mode: 3.89 W/3.31 W (max)
Standby mode (TTL): 57.6 mW (max)
Standby mode (CMOS)
: 14.4 mW (max)
: 4.32 mW (max) (L-version)
•
JEDEC standard outline S. O. DIMM
•
EDO page mode capability
HB56UW865DB-5/5L/6/6L
•
4096 refresh cycles:
64 ms
128 ms (L-version)
•
4 variations of refresh
RAS-only
refresh
CAS-before-RAS
refresh
Hidden refresh
Self refresh (L-version)
Ordering Information
Type No.
HB56UW865DB-5
HB56UW865DB-6
HB56UW865DB-5L
HB56UW865DB-6L
Access time
50 ns
60 ns
50 ns
60 ns
Package
Contact pad
144-pin small outline DIMM Gold
Pin Arrangement
Front Side
1pin
2pin
59pin
60pin
61pin
62pin
143pin
144pin
Back Side
Front side
Pin No.
1
3
5
Signal name Pin No.
V
SS
DQ0
DQ1
73
75
77
OE
V
SS
NC
Back side
Signal name Pin No.
2
4
6
Signal name Pin No.
V
SS
DQ32
DQ33
74
76
78
Signal name
NC
V
SS
NC
2
HB56UW865DB-5/5L/6/6L
Front side
Pin No.
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Signal name Pin No.
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
V
SS
CE0
CE1
V
CC
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
CC
DQ12
DQ13
DQ14
DQ15
V
SS
NC
NC
NC
V
CC
NC
WE
RE0
NC
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Back side
Signal name Pin No.
NC
V
CC
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
CC
A6
A8
V
SS
A9
A10
V
CC
CE2
CE3
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
CC
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Signal name Pin No.
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
V
SS
CE4
CE5
V
CC
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
CC
DQ44
DQ45
DQ46
DQ47
V
SS
NC
NC
NC
V
CC
NC
NC
NC
NC
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Signal name
NC
V
CC
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
V
CC
A7
A11
V
SS
NC
NC
V
CC
CE6
CE7
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
V
CC
3
HB56UW865DB-5/5L/6/6L
Pin Description
Pin name
A0 to A11
Function
Address input
Row address
A0 to A11
Column address A0 to A10
Refresh address A0 to A11
DQ0 to DQ63
RE0
CE0
to
CE7
WE
OE
SDA
SCL
V
CC
V
SS
NC
Data input/output
Row address strobe (RAS)
Column address strobe (CAS)
Read/Write enable
Output enable
Serial data for PD
Serial clock for PD
Power supply
Ground
No connection
4
HB56UW865DB-5/5L/6/6L
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
0
80
08
02
0C
0B
01
40
00
01
32
3C
0D
0F
00
00
83
08
00
00
00
01
2B
37
AE
BA
Future
offerings
Rev. 1
128
256 byte
EDO
12
11
1
64 bits
0 (+)
LVTTL
t
RAC
= 50 ns
t
RAC
= 60 ns
t
CAC
= 13 ns
t
CAC
= 15 ns
Non parity
Normal
(15.625
µs)
Self refresh
(31.3
µs)
8M
×
8
Number of row addresses bits 0
Number of column addresses bits
0
Number of banks
Module data width
0
0
Module data width (continued) 0
Module interface signal levels 0
RAS
access time
-5/5L
RAS
access time
-6/6L
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
10
CAS
access time
-5/5L
CAS
access time
-6/6L
11
12
Module configuration type
Refresh rate/type
-5/6
Refresh rate/type
-5L/6L (L-version)
13
14
DRAM width
Error checking DRAM data
width
15 to 31 Reserved for future offerings
32 to 61 Superset information
62
63
SPD revision
Checksum for bytes 0 to 62
-5
Checksum for bytes 0 to 62
-6
Checksum for bytes 0 to 62
-5L
Checksum for bytes 0 to 62
-6L
5
