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Customer Support Dept.
April 1, 2003
Cautions
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contained therein.
HD74AC157
Quad 2-Input Multiplexer
ADE-205-371 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC157 is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be
selected using the common Select and Enable inputs. The four outputs present the selected data in the true
(noninverted) form. The HD74AC157 can also be used as a function generator.
Feature
•
Outputs Source/Sink 24 mA
Pin Arrangement
S 1
I
0a
2
I
1a
3
Z
a
4
I
0b
5
I
1b
6
Z
b
7
GND 8
(Top view)
16 V
CC
15
E
14 I
0c
13 I
1c
12 Z
c
11 I
0d
10 I
1d
9 Z
d
HD74AC157
Logic Symbol
E
I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
od
I
1d
S
Z
a
Z
b
Z
c
Z
d
Pin Names
I
0a
to I
0d
I
1a
to I
1d
E
S
Z
a
to Z
d
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Outputs
Functional Description
The HD74AC157 is a quad 2-input multiplexer. It selects four bits of data from two sources under the
control of a common Select input (S). The Enable input (E) is active-Low. when
E
is High, all of the
outputs (Z) are forced Low regardless of all other inputs. The HD74AC157 is the logic implementation of
a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the
Select input. The logic equations for the outputs are shown below:
Z
a
=
E•(I
1a
•S + I
0a
•S)
Z
b
=
E•(I
1b
•S + I
0b
•S)
Z
c
=
E•(I
1c
•S + I
0c
•S)
Z
d
=
E•(I
1d
•S + I
0d
•S)
A common use of the HD74AC157 is the moving of data from two groups of register to four common
output busses. The particular register from which the data comes is determined by the state of the Select
input. A less obvious use is as a function generator. The HD74AC157 can generate any four of the sixteen
different functions of two variables with one variable common. This is useful for implementing gating
functions.
2
HD74AC157
Truth Table
Inputs
E
H
L
L
L
L
H :
L :
X :
S
X
H
H
L
L
High Voltage Level
Low Voltage Level
Immaterial
I
0
X
X
X
L
H
I
1
X
L
H
X
X
Output
Z
L
L
H
L
H
Logic Diagram
I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
E
S
Z
a
Z
b
Z
c
Z
d
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
3
