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HD74ACT112RP-EL

ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16

器件类别：逻辑    逻辑   

厂商名称：Renesas(瑞萨电子)

厂商官网：https://www.renesas.com/

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参数 预览 参数对比
器件参数
参数名称
属性值
零件包装代码
SOIC
包装说明
SOP,
针数
16
Reach Compliance Code
unknown
系列
ACT
JESD-30 代码
R-PDSO-G16
长度
9.9 mm
逻辑集成电路类型
J-K FLIP-FLOP
位数
2
功能数量
2
端子数量
16
最高工作温度
85 °C
最低工作温度
-40 °C
输出极性
COMPLEMENTARY
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
传播延迟（tpd）
14 ns
认证状态
Not Qualified
座面最大高度
1.75 mm
最大供电电压 (Vsup)
6 V
最小供电电压 (Vsup)
2 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
触发器类型
NEGATIVE EDGE
宽度
3.95 mm
最小 fmax
80 MHz
Base Number Matches
1
文档预览
HD74AC112/HD74ACT112
Dual JK Negative Edge-Triggered Flip-Flop
REJ03D0244–0200Z
(Previous ADE-205-364 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-
flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs
may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum
setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.
Features
•
Outputs Source/Sink 24 mA
•
HD74ACT112 has TTL-Compatible Inputs
•
Ordering Information: Ex. HD74AC112
Part Name
HD74AC112FPEL
HD74AC112RPEL
Package Type
SOP-16 pin (JEITA)
Package Code Package Abbreviation Taping Abbreviation (Quantity)
FP-16DAV
FP
RP
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
CP
1
1
K
1
2
J
1
3
S
D1
4
Q
1
5
Q
1
6
Q
2
7
GND 8
(Top view)
16 V
CC
15
C
D1
14
C
D2
13
CP
2
12 K
2
11 J
2
10
S
D2
9 Q
2
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC112/HD74ACT112
Logic Symbol
4
S
D1
11
13
Q
1
6 12
10
S
D2
3
1
2
J
1
Q
1
5
J
2
Q
2
9
CP
1
K
1
CP
2
K
2
Q
2
7
C
D1
15
C
D2
14
V
CC
= Pin16
GND = Pin8
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
,
CP
2
C
D1
,
C
D2
S
D1
,
S
D2
Q
1
, Q
2
,
Q
1
,
Q
2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Direct Set Inputs (Active Low)
Outputs
Asynchronous Inputs:
Low input to
S
D
sets Q to High level
Low input to
C
D
sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on
C
D
and
S
D
makes both Q and
Q
High
Truth Table
Inputs
@ t
n
J
L
L
H
H
t
n
t
n + 1
H
L
L
H
L
H
Bit time before clock pulse.
Bit time after clock pulse.
High Voltage Level
Low Voltage Level
K
Qn
L
H
Qn
Outputs
@ t
n + 1
Q
:
:
:
:
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC112/HD74ACT112
Logic Diagram
S
D
C
D
J
K
#
CP
#CP
Q
Q
CP
CP
#
CP
CP
#
CP
CP
#
CP
CP
CP
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Condition
Recommended Operating Conditions: HD74AC112
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
30% to 70% V
CC
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 3.0V
V
CC
= 4.5 V
V
CC
= 5.5 V
Unit
Condition
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC112/HD74ACT112
DC Characteristics: HD74AC112
Item
Sym-
bol
V
IH
Vcc
(V)
3.0
4.5
5.5
V
IL
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
V
OL
5.5
3.0
4.5
5.5
3.0
4.5
Input leakage
current
Dynamic output
current*
Quiescent supply
current
I
IN
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.58
3.94
4.94
—
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
0.002
0.001
0.001
—
—
—
—
—
—
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.32
0.32
0.32
±0.1
—
—
4.0
Ta = –40 to
+85°C
°
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
—
—
86
–75
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
40
µA
mA
mA
µA
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Unit
Condition
Input Voltage
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Output voltage
V
OH
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
or V
IH
I
OH
= –12 mA
I
OH
= –24 mA
I
OH
= –24 mA
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
IN
= V
CC
or GND
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
*Maximum
test duration 2.0 ms, one output loaded at a time.
Recommended Operating Conditions: HD74ACT112
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
0.8 to 2.0 V
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 4.5V
V
CC
= 5.5V
Unit
Condition
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC112/HD74ACT112
DC Characteristics: HD74ACT112
Item
Sym-
bol
V
IH
V
IL
Output voltage
V
OH
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
V
OL
5.5
4.5
5.5
4.5
Input current
I
CC
/input current
Dynamic output
current*
Quiescent supply
current
I
IN
I
CCT
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
5.5
min.
2.0
2.0
—
—
4.4
5.4
3.94
4.94
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
—
0.001
0.001
—
—
—
0.6
—
—
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.32
0.32
±0.1
—
—
—
4.0
Ta = –40 to
+85°C
°
min.
2.0
2.0
—
—
4.4
5.4
3.80
4.80
—
—
—
—
—
—
86
–75
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.37
0.37
±1.0
1.5
—
—
40
µA
mA
mA
mA
µA
V
Unit
Condition
Input voltage
V
V
OUT
= 0.1 V or Vcc–0.1 V
V
OUT
= 0.1 V or Vcc–0.1 V
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
V
IN
= V
CC
or GND
V
IN
= V
CC
–2.1 V
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
I
OL
= 24 mA
I
OL
= 24 mA
I
OH
= –24 mA
I
OH
= –24 mA
*Maximum
test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC112
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
C
P
to Q or
Q
Propagation delay
C
P
to Q or
Q
Propagation delay
C
D
,
S
D
to Q or
Q
Propagation delay
C
D
,
S
D
to Q or
Q
Note:
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
V
CC
(V)*
1
Min
3.3
125
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
150
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
11.0
8.5
11.0
8.5
9.5
7.0
11.5
9.0
Max
—
—
14.0
11.0
14.0
11.0
12.5
9.5
14.5
11.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
100
125
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
—
—
15.0
12.0
15.0
12.0
13.5
10.5
15.5
12.5
MHz
ns
Unit
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 7
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参数对比
与HD74ACT112RP-EL相近的元器件有：HD74AC112FP-EL、HD74AC112FPEL、HD74ACT112FP-EL、HD74ACT112FPEL、HD74ACT112RPEL、HD74ACT112FPVEL、HD74AC112RP-EL、HD74ACT112RPVEL。描述及对比如下：
型号 HD74ACT112RP-EL HD74AC112FP-EL HD74AC112FPEL HD74ACT112FP-EL HD74ACT112FPEL HD74ACT112RPEL HD74ACT112FPVEL HD74AC112RP-EL HD74ACT112RPVEL
描述 ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, LEAD FREE, SOP-16 AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SOP-16 ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, LEAD FREE, SOP-16
零件包装代码 SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC
包装说明 SOP, SOP, SOP-16 SOP, SOP-16 SOP, SOP16,.25 SOP, SOP, SOP,
针数 16 16 16 16 16 16 16 16 16
Reach Compliance Code unknown unknown compliant unknown compliant unknown unknown unknown compliant
系列 ACT AC AC ACT ACT ACT ACT AC ACT
JESD-30 代码 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
长度 9.9 mm 10.06 mm 10.06 mm 10.06 mm 10.06 mm 9.9 mm 10.06 mm 9.9 mm 9.9 mm
逻辑集成电路类型 J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP
位数 2 2 2 2 2 2 2 2 2
功能数量 2 2 2 2 2 2 2 2 2
端子数量 16 16 16 16 16 16 16 16 16
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
输出极性 COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SOP SOP SOP SOP SOP SOP SOP SOP SOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
传播延迟（tpd） 14 ns 15 ns 15 ns 14 ns 14 ns 14 ns 14 ns 15 ns 14 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.75 mm 2.2 mm 2.2 mm 2.2 mm 2.2 mm 1.75 mm 2.2 mm 1.75 mm 1.75 mm
最大供电电压 (Vsup) 6 V 6 V 6 V 6 V 6 V 6 V 6 V 6 V 6 V
最小供电电压 (Vsup) 2 V 2 V 2 V 2 V 2 V 2 V 2 V 2 V 2 V
标称供电电压 (Vsup) 5 V 3.3 V 3.3 V 5 V 5 V 5 V 5 V 3.3 V 5 V
表面贴装 YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
触发器类型 NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
宽度 3.95 mm 5.5 mm 5.5 mm 5.5 mm 5.5 mm 3.95 mm 5.5 mm 3.95 mm 3.95 mm
最小 fmax 80 MHz 125 MHz 125 MHz 80 MHz 80 MHz 80 MHz 80 MHz 125 MHz 80 MHz
Base Number Matches 1 1 1 1 1 1 1 1 1
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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