HANBit
HDD32M72B9
DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks,
8K Ref., ECC Unbuffered SO-DIMM
Part No. HDD32M72B9
GENERAL DESCRIPTION
The HDD32M72B9 is a 32M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.
The module consists of nine CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K
EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM. The HDD32M72B9 is a SO-DIMM(Small Outline Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance m emory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
•
Part Identification
HDD32M72B9
–
16B
HDD32M72B9
–
13A
HDD32M72B9
–
13B
:
:
:
166MHz (CL=2.5)
133MHz (CL=2)
133MHz (CL=2.5)
•
256MB(32Mx64) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRSM with ECC
•
2.5V
±
0.2V VDD and VDDQ power supply
•
Auto & self refresh capability (8192 Cycles/64ms)
•
All input and output are compatible with SSTL_2 interface
•
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
•
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
•
MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Burst type : Sequential & Interleave
•
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
•
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
•
The used device is 8M x 8bit x 4Banks DDR SDRAM
•
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
•
Serial Presence detect with EEPROM
URL : www.hbe.co.kr
REV 1.0 (July. 2003)
1
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
Back
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
PIN
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
Frontl
DQ27
VDD
CB0
CB1
Vss
DQS8
CB2
VDD
CB3
NC
VSS
CK2
/CK2
VDD
CKE1
NC(A13)
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
/WE
/CS0
NC
VSS
DQ32
DQ33
VDD
PIN
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
Back
DQ31
VDD
CB4
CB5
Vss
DM8
CB6
VDD
CB7
NC(/RESET)
VSS
VSS
VDD
VDD
CKE0
NC (BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
NC
NC
VSS
DQ36
DQ37
VDD
PIN
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
*These pins should be NC in the system which does not support SPD
PIN
PIN DESCRIPTION
PIN
A0~A12
BA0~BA1
DQ0~DQ63(CB0~CB7)
DQS0~DQS8
DM0~DM8
CK0~CK2,/CK0~/CK2
CKE0~CKE1
/CS0
/RAS, /CAS
NC
URL : www.hbe.co.kr
REV 1.0 (July. 2003)
HDD32M72B9
Front
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
PIN
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
*SA0
*SA1
*SA2
NC
PIN DESCRIPTION
Power supply(2.5V)
Power supply for DQs(2.5V)
Power supply for reference
Serial EEPROM Power supply(2.3V~3.3V)
Ground
Address in EEPROM
Serial data I/O
Serial clock
Write protection
VDD identification flag
HANBit Electronics Co.,Ltd.
Address input
Bank Select Address
Data input/output
(Check Bit Data In/Out)
Data Strobe input/output
Data-in Mask
Clock input
Clock enable input
Chip Select input
Row / Column Address strobe
No connection
2
VDD
VDDQ
VREF
VDDSPD
VSS
SA0~SA2
SDA
SCL
WP
VDDID
HANBit
FUNCTIONAL BLOCK DIAGRAM
HDD32M72B9
URL : www.hbe.co.kr
REV 1.0 (July. 2003)
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HANBit Electronics Co.,Ltd.
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PIN FUNCTION DESCRIPTION
Pin
CK, /CK
Clock
Name
HDD32M72B9
Input Function
CK and CK are differential clock inputs. All address and control input signals are
sam-pled on the positive edge of CK and negative edge of CK. Output (read) data
is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
CKE
Clock Enable
except for disabling outputs, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE are disabled during power-down and self refresh modes,
providing low standby power. CKE will recognizean LVCMOS LOW level prior to
VREF being stable on power-up.
CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external
/CS
Chip Select
bank selection on systems with multiple banks. CS is considered part of the
command code.
Row/column addresses are multiplexed on the same pins.
A0 ~ A12
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied.
Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe
Column
strobe
Write enable
address
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
Enables write operation and row precharge.
/CAS
/WE
Latches data in starting from /CAS, /WE active.
Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0 ~ 8
Data Strobe
tered in write data. Used to capture write data.
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~8
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the
DQ and DQS load-ing.
DQ0 ~ 63
CB0 ~ 7
VDDQ
VDD
VSS
Data input/output
Check Bit
Supply
Supply
Supply
Data inputs/outputs are multiplexed on the same pins.
Check Bits for ECC data are multiplexed on the same pins.
DQ Power Supply : +2.5V
±
0.2V.
Power Supply : +2.5V
±
0.2V (device specific).
DQ Ground.
VREF
VDDSPD
VDDID
Supply
Supply
SSTL_2 reference voltage.
Serial EEPROM Power Supply : 3.3v
VDD identification Flag
URL : www.hbe.co.kr
REV 1.0 (July. 2003)
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HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Voltage on V
DDQ
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
SYMBOL
V
IN
, V
OUT
V
DD
V
DDQ
T
STG
P
D
I
OS
RATING
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
8.0
50
HDD32M72B9
UNTE
V
V
V
°C
W
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 IN/OUT)
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70°C) )
PARAMETER
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage(system)
Input High Voltage
Input Low Voltage
Input Voltage Level, CK and /CK inputs
Input Differential Voltage, CK and /CK inputs
Input leakage current
Output leakage current
Output High current (Normal Strenth driver
(V
OUT
= V
TT
+ 0.84V)
Output Low current (Normal Strenth driver
(V
OUT
= V
TT -
0.84V)
Output High current (Normal Strenth driver
(V
OUT
= V
TT
+ 0.45V)
Output Low current (Normal Strenth driver
(V
OUT
= V
TT
- 0.45V)
Notes :
1. Includes
±
25mV margin for DC offset on VREF, and a combined total of
±
50mV margin for all AC noise and DC offset
on VREF,bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal
DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an
inductance of
¡
3nH.
Â
2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to
200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of
the same.
6. These charactericteristics obey the SSTL-2 class II standards.
I
OL
9
mA
I
OH
-9
I
OL
16.8
SYMBO
L
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
LI
I
OZ
I
OH
MIN
2.3
2.3
VDDQ/2-50mV
V
REF
–
0.04
V
REF
+ 0.15
-0.3
-0.3
0.3
-2
-5
-16.8
MAX
2.7
2.7
VDDQ/2+50mV
V
REF
+ 0.04
V
REF
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
2
5
UNIT
V
V
V
V
V
V
V
V
uA
uA
mA
3
5
1
2
4
4
NOTE
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REV 1.0 (July. 2003)
5
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