INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40174B
MSI
Hex D-type flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Hex D-type flip-flop
DESCRIPTION
The HEF40174B is a hex edge-triggered D-type flip-flop
with six data inputs (D
0
to D
5
), a clock input (CP), an
overriding asynchronous master reset input (MR), and six
HEF40174B
MSI
buffered outputs (O
0
to O
5
). Information on D
0
to D
5
is
transferred to O
0
to O
5
on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O
0
to O
5
= LOW) independent of CP and D
0
to D
5
.
Fig.1 Functional diagram.
PINNING
D
0
to D
5
CP
MR
O
0
to O
5
data inputs
clock input (LOW to HIGH; edge-triggered)
master reset input (active LOW)
buffered outputs
FUNCTION TABLE
Fig.2 Pinning diagram.
CP
HEF40174BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40174BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40174BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
X
INPUTS
D
H
L
X
X
MR
H
H
H
L
OUTPUT
O
H
L
no change
L
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Philips Semiconductors
January 1995
Hex D-type flip-flop
3
HEF40174B
MSI
Product specification
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
Hex D-type flip-flop
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
MR
→
O
n
HIGH to LOW
Output transition times
HIGH to LOW
10
15
5
10
15
5
10
15
5
LOW to HIGH
Set-up time
D
n
→
CP
Hold time
D
n
→
CP
Minimum clock
pulse width; LOW
Minimum MR pulse
width; LOW
Recovery time
for MR
Maximum clock
pulse frequency
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
f
max
t
RMR
t
WMRL
t
WCPL
t
hold
t
su
20
10
10
10
5
5
70
30
20
70
35
25
45
20
15
5
15
20
t
TLH
t
THL
t
PHL
t
PLH
t
PHL
75
30
20
75
30
20
85
35
25
60
30
20
60
30
20
10
5
5
0
0
0
35
15
10
35
15
10
25
10
5
11
30
45
155 ns
65 ns
45 ns
155 ns
65 ns
45 ns
175 ns
70 ns
50 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
SYMBOL
MIN. TYP. MAX.
HEF40174B
MSI
TYPICAL EXTRAPOLATION
FORMULA
48 ns
+
(0,55 ns/pF) C
L
19 ns
+
(0,23 ns/pF) C
L
12 ns
+
(0,16 ns/pF) C
L
48 ns
+
(0,55 ns/pF) C
L
19 ns
+
(0,23 ns/pF) C
L
12 ns
+
(0,16 ns/pF) C
L
58 ns
+
(0,55 ns/pF) C
L
24 ns
+
(0,23 ns/pF) C
L
17 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
see also waveforms
Fig.4
January 1995
4
Philips Semiconductors
Product specification
Hex D-type flip-flop
HEF40174B
MSI
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P(µW)
3500 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
16 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
42 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
Fig.4
Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and
hold time for D
n
to CP. Set-up and hold times are shown as positive values but may be specified as
negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF40174B are:
•
Shift registers
•
Buffer/storage register
•
Pattern generator
January 1995
5
单片机
