INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40192B
MSI
4-bit up/down decade counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
4-bit up/down decade counter
DESCRIPTION
The HEF40192B is a 4-bit synchronous up/down decade
counter. The counter has a count-up clock input (CP
U
), a
count-down clock input (CP
D
), an asynchronous parallel
load input (PL), four parallel data inputs (P
0
to P
3
), an
asynchronous master reset input (MR), four counter
outputs (O
0
to O
3
), an active LOW terminal count-up
(carry) output (TC
U
) and an active LOW terminal
count-down (borrow) output (TC
D
).
The counter outputs change state on the LOW to HIGH
transition of either clock input. However, for correct
HEF40192B
MSI
counting, both clock inputs cannot be LOW
simultaneously. The outputs TC
U
and TC
D
are normally
HIGH. When the circuit has reached the maximum count
state of ‘9’, the next HIGH to LOW transition of CP
U
will
cause TC
U
to go LOW. TC
U
will stay LOW until CP
U
goes
HIGH again. Likewise, output TC
D
will go LOW when the
circuit is in the zero state and CP
D
goes LOW. When PL is
LOW, the information on P
0
to P
3
is asynchronously
loaded into the counter. A HIGH on MR resets the counter
independent of all other input conditions. The counter
stages are of a static toggle type flip-flop.
Fig.2 Pinning diagram.
HEF40192BP(N): 16-lead DIL; plastic
(SOT38-1)
Fig.1 Functional diagram.
HEF40192BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40192BT(D): 16-lead SO; plastic
PINNING
PL
P
0
to P
3
CP
U
CP
D
MR
TC
U
TC
D
O
0
to O
3
parallel load input (active LOW)
parallel data inputs
count-up clock pulse input (LOW to HIGH,
edge-triggered)
count-down clock pulse input (LOW to
HIGH, edge-triggered)
master reset input (asynchronous)
buffered terminal count-up (carry) output
(active LOW)
buffered terminal count-down
(borrow) output (active LOW)
buffered counter outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
(SOT109-1)
( ): Package Designator North America
January 1995
2
Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B
MSI
Fig.3 Logic diagram (continued on next page).
January 1995
3
Philips Semiconductors
Product specification
4-bit up/down decade counter
HEF40192B
MSI
Fig.4 Logic diagram (continued from Fig.3).
January 1995
4
Philips Semiconductors
Product specification
4-bit up/down decade counter
FUNCTION TABLE
MR
H
L
L
L
PL
X
L
H
H
H
CP
U
X
X
CP
D
X
X
H
MODE
reset (asyn.)
parallel load
count-up
count-down
Notes
HEF40192B
MSI
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
Logic equations for terminal count:
TC
D
=
O
0
⋅
O
1
⋅
O
2
⋅
O
3
⋅
CP
D
TC
U
=
O
0
⋅
O
3
⋅
CP
U
Fig.5 State diagram.
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
550 f
i
+ ∑(f
o
C
L
)
×
V
DD2
2400 f
i
+ ∑(f
o
C
L
)
×
V
DD2
6500 f
i
+ ∑(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
5
DSP 与 ARM 处理器
